1c5fa550e8
pessimal (u_short) types for i/o ports. I don't understand the data structures in this driver well enough to unpessimize the types.
454 lines
18 KiB
C
454 lines
18 KiB
C
/*
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* Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
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* controller RISC processor CL-CD2400/2401.
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*
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* Copyright (C) 1994 Cronyx Ltd.
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* Author: Serge Vakulenko, <vak@zebub.msk.su>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
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* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Authors grant any other persons or organizations permission to use
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* or modify this software as long as this message is kept with the software,
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* all derivative works or modified versions.
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*
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* Version 1.0, Fri Oct 7 19:34:06 MSD 1994
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* $FreeBSD$
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*/
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#define NBRD 3 /* the maximum number of installed boards */
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#define NPORT 16 /* the number of i/o ports per board */
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#define REVCL_MIN 7 /* CD2400 min. revision number G */
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#define REVCL_MAX 11 /* CD2400 max. revision number K */
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#define BRD_INTR_LEVEL 0x5a /* interrupt level (arbitrary PILR value) */
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#define CS0(p) ((p) | 0x8000) /* chip select 0 */
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#define CS1(p) ((p) | 0xc000) /* chip select 1 */
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#define BSR(p) (p) /* board status register, read only */
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#define BCR0(p) (p) /* board command register 0, write only */
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#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */
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/*
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* Chip register address, B is chip base port, R is chip register number.
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*/
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#define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
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/*
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* Interrupt acknowledge register, P is board port, L is interrupt level,
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* as programmed in PILR.
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*/
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#define IACK(p,l) (R(p,l) | 0x4000)
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/*
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* Global registers.
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*/
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#define GFRCR(b) R(b,0x82) /* global firmware revision code register */
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#define CAR(b) R(b,0xec) /* channel access register */
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/*
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* Option registers.
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*/
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#define CMR(b) R(b,0x18) /* channel mode register */
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#define COR1(b) R(b,0x13) /* channel option register 1 */
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#define COR2(b) R(b,0x14) /* channel option register 2 */
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#define COR3(b) R(b,0x15) /* channel option register 3 */
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#define COR4(b) R(b,0x16) /* channel option register 4 */
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#define COR5(b) R(b,0x17) /* channel option register 5 */
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#define COR6(b) R(b,0x1b) /* channel option register 6 */
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#define COR7(b) R(b,0x04) /* channel option register 7 */
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#define SCHR1(b) R(b,0x1c) /* special character register 1 */
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#define SCHR2(b) R(b,0x1d) /* special character register 2 */
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#define SCHR3(b) R(b,0x1e) /* special character register 3 */
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#define SCHR4(b) R(b,0x1f) /* special character register 4 */
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#define SCRL(b) R(b,0x20) /* special character range low */
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#define SCRH(b) R(b,0x21) /* special character range high */
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#define LNXT(b) R(b,0x2d) /* LNext character */
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#define RFAR1(b) R(b,0x1c) /* receive frame address register 1 */
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#define RFAR2(b) R(b,0x1d) /* receive frame address register 2 */
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#define RFAR3(b) R(b,0x1e) /* receive frame address register 3 */
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#define RFAR4(b) R(b,0x1f) /* receive frame address register 4 */
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#define CPSR(b) R(b,0xd4) /* CRC polynomial select register */
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/*
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* Bit rate and clock option registers.
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*/
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#define RBPR(b) R(b,0xc9) /* receive baud rate period register */
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#define RCOR(b) R(b,0xca) /* receive clock option register */
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#define TBPR(b) R(b,0xc1) /* transmit baud rate period register */
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#define TCOR(b) R(b,0xc2) /* receive clock option register */
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/*
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* Channel command and status registers.
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*/
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#define CCR(b) R(b,0x10) /* channel command register */
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#define STCR(b) R(b,0x11) /* special transmit command register */
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#define CSR(b) R(b,0x19) /* channel status register */
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#define MSVR(b) R(b,0xdc) /* modem signal value register */
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#define MSVR_RTS(b) R(b,0xdc) /* modem RTS setup register */
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#define MSVR_DTR(b) R(b,0xdd) /* modem DTR setup register */
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/*
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* Interrupt registers.
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*/
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#define LIVR(b) R(b,0x0a) /* local interrupt vector register */
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#define IER(b) R(b,0x12) /* interrupt enable register */
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#define LICR(b) R(b,0x25) /* local interrupting channel register */
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#define STK(b) R(b,0xe0) /* stack register */
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/*
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* Receive interrupt registers.
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*/
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#define RPILR(b) R(b,0xe3) /* receive priority interrupt level register */
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#define RIR(b) R(b,0xef) /* receive interrupt register */
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#define RISR(b) R(b,0x8a) /* receive interrupt status register */
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#define RISRL(b) R(b,0x8a) /* receive interrupt status register low */
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#define RISRH(b) R(b,0x8b) /* receive interrupt status register high */
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#define RFOC(b) R(b,0x33) /* receive FIFO output count */
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#define RDR(b) R(b,0xf8) /* receive data register */
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#define REOIR(b) R(b,0x87) /* receive end of interrupt register */
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/*
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* Transmit interrupt registers.
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*/
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#define TPILR(b) R(b,0xe2) /* transmit priority interrupt level reg */
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#define TIR(b) R(b,0xee) /* transmit interrupt register */
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#define TISR(b) R(b,0x89) /* transmit interrupt status register */
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#define TFTC(b) R(b,0x83) /* transmit FIFO transfer count */
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#define TDR(b) R(b,0xf8) /* transmit data register */
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#define TEOIR(b) R(b,0x86) /* transmit end of interrupt register */
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/*
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* Modem interrupt registers.
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*/
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#define MPILR(b) R(b,0xe1) /* modem priority interrupt level register */
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#define MIR(b) R(b,0xed) /* modem interrupt register */
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#define MISR(b) R(b,0x88) /* modem/timer interrupt status register */
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#define MEOIR(b) R(b,0x85) /* modem end of interrupt register */
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/*
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* DMA registers.
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*/
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#define DMR(b) R(b,0xf4) /* DMA mode register */
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#define BERCNT(b) R(b,0x8d) /* bus error retry count */
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#define DMABSTS(b) R(b,0x1a) /* DMA buffer status */
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/*
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* DMA receive registers.
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*/
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#define ARBADRL(b) R(b,0x40) /* A receive buffer address lower */
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#define ARBADRU(b) R(b,0x42) /* A receive buffer address upper */
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#define BRBADRL(b) R(b,0x44) /* B receive buffer address lower */
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#define BRBADRU(b) R(b,0x46) /* B receive buffer address upper */
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#define ARBCNT(b) R(b,0x48) /* A receive buffer byte count */
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#define BRBCNT(b) R(b,0x4a) /* B receive buffer byte count */
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#define ARBSTS(b) R(b,0x4c) /* A receive buffer status */
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#define BRBSTS(b) R(b,0x4d) /* B receive buffer status */
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#define RCBADRL(b) R(b,0x3c) /* receive current buffer address lower */
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#define RCBADRU(b) R(b,0x3e) /* receive current buffer address upper */
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/*
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* DMA transmit registers.
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*/
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#define ATBADRL(b) R(b,0x50) /* A transmit buffer address lower */
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#define ATBADRU(b) R(b,0x52) /* A transmit buffer address upper */
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#define BTBADRL(b) R(b,0x54) /* B transmit buffer address lower */
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#define BTBADRU(b) R(b,0x56) /* B transmit buffer address upper */
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#define ATBCNT(b) R(b,0x58) /* A transmit buffer byte count */
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#define BTBCNT(b) R(b,0x5a) /* B transmit buffer byte count */
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#define ATBSTS(b) R(b,0x5c) /* A transmit buffer status */
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#define BTBSTS(b) R(b,0x5d) /* B transmit buffer status */
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#define TCBADRL(b) R(b,0x38) /* transmit current buffer address lower */
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#define TCBADRU(b) R(b,0x3a) /* transmit current buffer address upper */
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/*
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* Timer registers.
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*/
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#define TPR(b) R(b,0xd8) /* timer period register */
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#define RTPR(b) R(b,0x26) /* receive timeout period register */
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#define RTPRL(b) R(b,0x26) /* receive timeout period register low */
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#define RTPTH(b) R(b,0x27) /* receive timeout period register high */
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#define GT1(b) R(b,0x28) /* general timer 1 */
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#define GT1L(b) R(b,0x28) /* general timer 1 low */
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#define GT1H(b) R(b,0x29) /* general timer 1 high */
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#define GT2(b) R(b,0x2a) /* general timer 2 */
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#define TTR(b) R(b,0x2a) /* transmit timer register */
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/*
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* Board status register bits.
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*/
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#define BSR_NOINTR 0x01 /* no interrupt pending flag */
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#define BSR_VAR_MASK 0x66 /* adapter variant mask */
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#define BSR_OSC_MASK 0x18 /* oscillator frequency mask */
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#define BSR_OSC_20 0x18 /* 20 MHz */
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#define BSR_OSC_18432 0x10 /* 18.432 MHz */
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#define BSR_NOCHAIN 0x80 /* no daisy chained board */
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#define BSR_NODSR(n) (0x100 << (n)) /* DSR from channels 0-3, inverted */
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#define BSR_NOCD(n) (0x1000 << (n)) /* CD from channels 0-3, inverted */
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/*
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* Board revision mask.
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*/
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#define BSR_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
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/*
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* Board control register 0 bits.
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*/
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#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */
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#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */
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#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */
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#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */
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#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */
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#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */
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#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */
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#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */
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#define BCR0_NORESET 0x08 /* CD2400 reset flag (inverted) */
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#define BCR0_DMA_DIS 0x00 /* no interrupt generated */
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#define BCR0_DMA_5 0x10 /* select DMA channel 5 */
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#define BCR0_DMA_6 0x20 /* select DMA channel 6 */
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#define BCR0_DMA_7 0x30 /* select DMA channel 7 */
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#define BCR0_UM_ASYNC 0x00 /* channel 0 mode - async */
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#define BCR0_UM_SYNC 0x80 /* channel 0 mode - sync */
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#define BCR0_UI_RS232 0x00 /* channel 0 interface - RS-232 */
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#define BCR0_UI_RS449 0x40 /* channel 0 interface - RS-449/V.35 */
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#define BCR0_UMASK 0xc0 /* channel 0 interface mask */
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/*
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* Board control register 1 bits.
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*/
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#define BCR1_DTR(n) (0x100 << (n)) /* DTR for channels 0-3 sync */
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/*
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* Cronyx board variants.
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*/
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#define CRONYX_100 0x64
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#define CRONYX_400 0x62
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#define CRONYX_500 0x60
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#define CRONYX_410 0x24
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#define CRONYX_810 0x20
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#define CRONYX_410s 0x04
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#define CRONYX_810s 0x00
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#define CRONYX_440 0x44
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#define CRONYX_840 0x40
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#define CRONYX_401 0x26
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#define CRONYX_801 0x22
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#define CRONYX_401s 0x06
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#define CRONYX_801s 0x02
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#define CRONYX_404 0x46
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#define CRONYX_703 0x42
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/*
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* Channel commands (CCR).
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*/
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#define CCR_CLRCH 0x40 /* clear channel */
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#define CCR_INITCH 0x20 /* initialize channel */
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#define CCR_RSTALL 0x10 /* reset all channels */
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#define CCR_ENTX 0x08 /* enable transmitter */
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#define CCR_DISTX 0x04 /* disable transmitter */
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#define CCR_ENRX 0x02 /* enable receiver */
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#define CCR_DISRX 0x01 /* disable receiver */
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#define CCR_CLRT1 0xc0 /* clear timer 1 */
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#define CCR_CLRT2 0xa0 /* clear timer 2 */
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#define CCR_CLRRCV 0x90 /* clear receiver */
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/*
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* Interrupt enable register (IER) bits.
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*/
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#define IER_MDM 0x80 /* modem status changed */
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#define IER_RET 0x20 /* receive exception timeout */
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#define IER_RXD 0x08 /* data received */
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#define IER_TIMER 0x04 /* timer expired */
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#define IER_TXMPTY 0x02 /* transmitter empty */
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#define IER_TXD 0x01 /* data transmitted */
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/*
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* Modem signal values register bits (MSVR).
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*/
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#define MSV_DSR 0x80 /* state of Data Set Ready input */
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#define MSV_CD 0x40 /* state of Carrier Detect input */
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#define MSV_CTS 0x20 /* state of Clear to Send input */
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#define MSV_TXCOUT 0x10 /* TXCout/DTR pin output flag */
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#define MSV_PORTID 0x04 /* device is CL-CD2401 (not 2400) */
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#define MSV_DTR 0x02 /* state of Data Terminal Ready output */
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#define MSV_RTS 0x01 /* state of Request to Send output */
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#define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
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/*
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* DMA buffer status register bits (DMABSTS).
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*/
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#define DMABSTS_TDALIGN 0x80 /* internal data alignment in transmit FIFO */
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#define DMABSTS_RSTAPD 0x40 /* reset append mode */
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#define DMABSTS_CRTTBUF 0x20 /* internal current transmit buffer in use */
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#define DMABSTS_APPEND 0x10 /* append buffer is in use */
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#define DMABSTS_NTBUF 0x08 /* next transmit buffer is B (not A) */
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#define DMABSTS_TBUSY 0x04 /* current transmit buffer is in use */
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#define DMABSTS_NRBUF 0x02 /* next receive buffer is B (not A) */
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#define DMABSTS_RBUSY 0x01 /* current receive buffer is in use */
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/*
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* Buffer status register bits ([AB][RT]BSTS).
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*/
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#define BSTS_BUSERR 0x80 /* bus error */
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#define BSTS_EOFR 0x40 /* end of frame */
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#define BSTS_EOBUF 0x20 /* end of buffer */
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#define BSTS_APPEND 0x08 /* append mode */
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#define BSTS_INTR 0x02 /* interrupt required */
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#define BSTS_OWN24 0x01 /* buffer is (free to be) used by CD2400 */
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#define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr"
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/*
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* Receive interrupt status register (RISR) bits.
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*/
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#define RIS_OVERRUN 0x0008 /* overrun error */
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#define RIS_BB 0x0800 /* buffer B status (not A) */
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#define RIS_EOBUF 0x2000 /* end of buffer reached */
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#define RIS_EOFR 0x4000 /* frame reception complete */
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#define RIS_BUSERR 0x8000 /* bus error */
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#define RISH_CLRDCT 0x0001 /* X.21 clear detect */
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#define RISH_RESIND 0x0004 /* residual indication */
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#define RISH_CRCERR 0x0010 /* CRC error */
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#define RISH_RXABORT 0x0020 /* abort sequence received */
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#define RISH_EOFR 0x0040 /* complete frame received */
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#define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
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#define RISA_BREAK 0x0001 /* break signal detected */
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#define RISA_FRERR 0x0002 /* frame error (bad stop bits) */
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#define RISA_PARERR 0x0004 /* parity error */
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#define RISA_SCMASK 0x0070 /* special character detect mask */
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#define RISA_SCHR1 0x0010 /* special character 1 detected */
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#define RISA_SCHR2 0x0020 /* special character 2 detected */
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#define RISA_SCHR3 0x0030 /* special character 3 detected */
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#define RISA_SCHR4 0x0040 /* special character 4 detected */
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#define RISA_SCRANGE 0x0070 /* special character in range detected */
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#define RISA_TIMEOUT 0x0080 /* receive timeout, no data */
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#define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
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#define RISB_CRCERR 0x0010 /* CRC error */
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#define RISB_RXABORT 0x0020 /* abort sequence received */
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#define RISB_EOFR 0x0040 /* complete frame received */
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#define RISX_LEADCHG 0x0001 /* CTS lead change */
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#define RISX_PARERR 0x0004 /* parity error */
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#define RISX_SCMASK 0x0070 /* special character detect mask */
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#define RISX_SCHR1 0x0010 /* special character 1 detected */
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#define RISX_SCHR2 0x0020 /* special character 2 detected */
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#define RISX_SCHR3 0x0030 /* special character 3 detected */
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#define RISX_ALLZERO 0x0040 /* all 0 condition detected */
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#define RISX_ALLONE 0x0050 /* all 1 condition detected */
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#define RISX_ALTOZ 0x0060 /* alternating 1 0 condition detected */
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#define RISX_SYN 0x0070 /* SYN detected */
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#define RISX_LEAD 0x0080 /* leading value */
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/*
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* Channel mode register (CMR) bits.
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*/
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#define CMR_RXDMA 0x80 /* DMA receive transfer mode */
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#define CMR_TXDMA 0x40 /* DMA transmit transfer mode */
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#define CMR_HDLC 0x00 /* HDLC protocol mode */
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#define CMR_BISYNC 0x01 /* BISYNC protocol mode */
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#define CMR_ASYNC 0x02 /* ASYNC protocol mode */
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#define CMR_X21 0x03 /* X.21 protocol mode */
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/*
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* Modem interrupt status register (MISR) bits.
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*/
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#define MIS_CDSR 0x80 /* DSR changed */
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#define MIS_CCD 0x40 /* CD changed */
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#define MIS_CCTS 0x20 /* CTS changed */
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#define MIS_CGT2 0x02 /* GT2 timer expired */
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#define MIS_CGT1 0x01 /* GT1 timer expired */
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#define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr"
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/*
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* Transmit interrupt status register (TISR) bits.
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*/
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#define TIS_BUSERR 0x80 /* Bus error */
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#define TIS_EOFR 0x40 /* End of frame */
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#define TIS_EOBUF 0x20 /* end of transmit buffer reached */
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#define TIS_UNDERRUN 0x10 /* transmit underrun */
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#define TIS_BB 0x08 /* buffer B status (not A) */
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#define TIS_TXEMPTY 0x02 /* transmitter empty */
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#define TIS_TXDATA 0x01 /* transmit data below threshold */
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#define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
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/*
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* Local interrupt vector register (LIVR) bits.
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*/
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#define LIV_EXCEP 0
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#define LIV_MODEM 1
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#define LIV_TXDATA 2
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#define LIV_RXDATA 3
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/*
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|
* Transmit end of interrupt registers (TEOIR) bits.
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*/
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#define TEOI_TERMBUFF 0x80 /* force current buffer to be discarded */
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#define TEOI_EOFR 0x40 /* end of frame in interrupt mode */
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|
#define TEOI_SETTM2 0x20 /* set general timer 2 in sync mode */
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#define TEOI_SETTM1 0x10 /* set general timer 1 in sync mode */
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#define TEOI_NOTRANSF 0x08 /* no transfer of data on this interrupt */
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|
|
|
/*
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* Receive end of interrupt registers (REOIR) bits.
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|
*/
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|
#define REOI_TERMBUFF 0x80 /* force current buffer to be terminated */
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|
#define REOI_DISCEXC 0x40 /* discard exception character */
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#define REOI_SETTM2 0x20 /* set general timer 2 */
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|
#define REOI_SETTM1 0x10 /* set general timer 1 */
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|
#define REOI_NOTRANSF 0x08 /* no transfer of data */
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|
#define REOI_GAP_MASK 0x07 /* optional gap size to leave in buffer */
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|
|
|
/*
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|
* Special transmit command register (STCR) bits.
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|
*/
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|
#define STC_ABORTTX 0x40 /* abort transmission (HDLC mode) */
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|
#define STC_APPDCMP 0x20 /* append complete (async DMA mode) */
|
|
#define STC_SNDSPC 0x08 /* send special characters (async mode) */
|
|
#define STC_SSPC_MASK 0x07 /* special character select */
|
|
#define STC_SSPC_1 0x01 /* send special character #1 */
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|
#define STC_SSPC_2 0x02 /* send special character #2 */
|
|
#define STC_SSPC_3 0x03 /* send special character #3 */
|
|
#define STC_SSPC_4 0x04 /* send special character #4 */
|
|
|
|
/*
|
|
* Channel status register (CSR) bits, asynchronous mode.
|
|
*/
|
|
#define CSRA_RXEN 0x80 /* receiver enable */
|
|
#define CSRA_RXFLOFF 0x40 /* receiver flow off */
|
|
#define CSRA_RXFLON 0x20 /* receiver flow on */
|
|
#define CSRA_TXEN 0x08 /* transmitter enable */
|
|
#define CSRA_TXFLOFF 0x04 /* transmitter flow off */
|
|
#define CSRA_TXFLON 0x02 /* transmitter flow on */
|
|
#define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"
|
|
|
|
/*
|
|
* Hacks to avoid inb() and outb()'s checks that the port type is not
|
|
* pessimal.
|
|
*/
|
|
|
|
static __inline u_char
|
|
xinb(u_int port)
|
|
{
|
|
return (inb(port));
|
|
}
|
|
|
|
#undef inb
|
|
#define inb(port) xinb(port)
|
|
|
|
static __inline void
|
|
xoutb(u_int port, u_char data)
|
|
{
|
|
outb(port, data);
|
|
}
|
|
|
|
#undef outb
|
|
#define outb(port, data) xoutb((port), (data))
|