321 lines
12 KiB
C++
321 lines
12 KiB
C++
//===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register bank for a code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include "CodeGenRegisters.h"
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#define DEBUG_TYPE "register-bank-emitter"
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using namespace llvm;
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namespace {
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class RegisterBank {
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/// A vector of register classes that are included in the register bank.
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typedef std::vector<const CodeGenRegisterClass *> RegisterClassesTy;
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private:
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const Record &TheDef;
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/// The register classes that are covered by the register bank.
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RegisterClassesTy RCs;
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/// The register class with the largest register size.
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const CodeGenRegisterClass *RCWithLargestRegsSize;
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public:
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RegisterBank(const Record &TheDef)
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: TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
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/// Get the human-readable name for the bank.
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StringRef getName() const { return TheDef.getValueAsString("Name"); }
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/// Get the name of the enumerator in the ID enumeration.
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std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
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/// Get the name of the array holding the register class coverage data;
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std::string getCoverageArrayName() const {
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return (TheDef.getName() + "CoverageData").str();
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}
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/// Get the name of the global instance variable.
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StringRef getInstanceVarName() const { return TheDef.getName(); }
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const Record &getDef() const { return TheDef; }
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/// Get the register classes listed in the RegisterBank.RegisterClasses field.
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std::vector<const CodeGenRegisterClass *>
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getExplictlySpecifiedRegisterClasses(
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CodeGenRegBank &RegisterClassHierarchy) const {
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std::vector<const CodeGenRegisterClass *> RCs;
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for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
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RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
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return RCs;
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}
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/// Add a register class to the bank without duplicates.
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void addRegisterClass(const CodeGenRegisterClass *RC) {
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if (std::find_if(RCs.begin(), RCs.end(),
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[&RC](const CodeGenRegisterClass *X) {
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return X == RC;
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}) != RCs.end())
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return;
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// FIXME? We really want the register size rather than the spill size
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// since the spill size may be bigger on some targets with
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// limited load/store instructions. However, we don't store the
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// register size anywhere (we could sum the sizes of the subregisters
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// but there may be additional bits too) and we can't derive it from
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// the VT's reliably due to Untyped.
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if (RCWithLargestRegsSize == nullptr)
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RCWithLargestRegsSize = RC;
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else if (RCWithLargestRegsSize->SpillSize < RC->SpillSize)
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RCWithLargestRegsSize = RC;
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assert(RCWithLargestRegsSize && "RC was nullptr?");
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RCs.emplace_back(RC);
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}
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const CodeGenRegisterClass *getRCWithLargestRegsSize() const {
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return RCWithLargestRegsSize;
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}
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iterator_range<typename RegisterClassesTy::const_iterator>
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register_classes() const {
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return llvm::make_range(RCs.begin(), RCs.end());
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}
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};
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class RegisterBankEmitter {
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private:
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RecordKeeper &Records;
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CodeGenRegBank RegisterClassHierarchy;
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void emitHeader(raw_ostream &OS, const StringRef TargetName,
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const std::vector<RegisterBank> &Banks);
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void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
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const std::vector<RegisterBank> &Banks);
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void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
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std::vector<RegisterBank> &Banks);
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public:
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RegisterBankEmitter(RecordKeeper &R)
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: Records(R), RegisterClassHierarchy(Records) {}
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void run(raw_ostream &OS);
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};
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} // end anonymous namespace
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/// Emit code to declare the ID enumeration and external global instance
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/// variables.
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void RegisterBankEmitter::emitHeader(raw_ostream &OS,
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const StringRef TargetName,
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const std::vector<RegisterBank> &Banks) {
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// <Target>RegisterBankInfo.h
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OS << "namespace llvm {\n"
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<< "namespace " << TargetName << " {\n"
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<< "enum {\n";
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for (const auto &Bank : Banks)
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OS << " " << Bank.getEnumeratorName() << ",\n";
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OS << " NumRegisterBanks,\n"
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<< "};\n"
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<< "} // end namespace " << TargetName << "\n"
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<< "} // end namespace llvm\n";
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}
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/// Emit declarations of the <Target>GenRegisterBankInfo class.
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void RegisterBankEmitter::emitBaseClassDefinition(
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raw_ostream &OS, const StringRef TargetName,
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const std::vector<RegisterBank> &Banks) {
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OS << "private:\n"
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<< " static RegisterBank *RegBanks[];\n\n"
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<< "protected:\n"
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<< " " << TargetName << "GenRegisterBankInfo();\n"
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<< "\n";
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}
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/// Visit each register class belonging to the given register bank.
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///
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/// A class belongs to the bank iff any of these apply:
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/// * It is explicitly specified
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/// * It is a subclass of a class that is a member.
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/// * It is a class containing subregisters of the registers of a class that
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/// is a member. This is known as a subreg-class.
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///
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/// This function must be called for each explicitly specified register class.
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///
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/// \param RC The register class to search.
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/// \param Kind A debug string containing the path the visitor took to reach RC.
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/// \param VisitFn The action to take for each class visited. It may be called
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/// multiple times for a given class if there are multiple paths
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/// to the class.
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static void visitRegisterBankClasses(
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CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
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const Twine Kind,
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std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
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SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
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// Make sure we only visit each class once to avoid infinite loops.
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if (VisitedRCs.count(RC))
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return;
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VisitedRCs.insert(RC);
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// Visit each explicitly named class.
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VisitFn(RC, Kind.str());
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for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
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std::string TmpKind =
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(Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();
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// Visit each subclass of an explicitly named class.
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if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
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visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
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TmpKind + " " + RC->getName() + " subclass",
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VisitFn, VisitedRCs);
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// Visit each class that contains only subregisters of RC with a common
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// subregister-index.
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//
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// More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
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// PossibleSubclass for all registers Reg from RC using any
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// subregister-index SubReg
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for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
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BitVector BV(RegisterClassHierarchy.getRegClasses().size());
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PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
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if (BV.test(RC->EnumValue)) {
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std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
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" class-with-subregs: " + RC->getName())
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.str();
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VisitFn(&PossibleSubclass, TmpKind2);
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}
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}
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}
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}
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void RegisterBankEmitter::emitBaseClassImplementation(
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raw_ostream &OS, StringRef TargetName,
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std::vector<RegisterBank> &Banks) {
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OS << "namespace llvm {\n"
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<< "namespace " << TargetName << " {\n";
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for (const auto &Bank : Banks) {
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std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
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(RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
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for (const auto &RC : Bank.register_classes())
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RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
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OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
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unsigned LowestIdxInWord = 0;
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for (const auto &RCs : RCsGroupedByWord) {
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OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
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for (const auto &RC : RCs) {
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std::string QualifiedRegClassID =
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(Twine(TargetName) + "::" + RC->getName() + "RegClassID").str();
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OS << " (1u << (" << QualifiedRegClassID << " - "
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<< LowestIdxInWord << ")) |\n";
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}
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OS << " 0,\n";
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LowestIdxInWord += 32;
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}
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OS << "};\n";
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}
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OS << "\n";
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for (const auto &Bank : Banks) {
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std::string QualifiedBankID =
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(TargetName + "::" + Bank.getEnumeratorName()).str();
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unsigned Size = Bank.getRCWithLargestRegsSize()->SpillSize;
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OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
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<< QualifiedBankID << ", /* Name */ \"" << Bank.getName()
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<< "\", /* Size */ " << Size << ", "
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<< "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
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<< ", /* NumRegClasses */ "
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<< RegisterClassHierarchy.getRegClasses().size() << ");\n";
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}
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OS << "} // end namespace " << TargetName << "\n"
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<< "\n";
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OS << "RegisterBank *" << TargetName
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<< "GenRegisterBankInfo::RegBanks[] = {\n";
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for (const auto &Bank : Banks)
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OS << " &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";
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OS << "};\n\n";
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OS << TargetName << "GenRegisterBankInfo::" << TargetName
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<< "GenRegisterBankInfo()\n"
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<< " : RegisterBankInfo(RegBanks, " << TargetName
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<< "::NumRegisterBanks) {\n"
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<< " // Assert that RegBank indices match their ID's\n"
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<< "#ifndef NDEBUG\n"
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<< " unsigned Index = 0;\n"
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<< " for (const auto &RB : RegBanks)\n"
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<< " assert(Index++ == RB->getID() && \"Index != ID\");\n"
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<< "#endif // NDEBUG\n"
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<< "}\n"
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<< "} // end namespace llvm\n";
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}
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void RegisterBankEmitter::run(raw_ostream &OS) {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() != 1)
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PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
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StringRef TargetName = Targets[0]->getName();
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std::vector<RegisterBank> Banks;
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for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
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SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
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RegisterBank Bank(*V);
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for (const CodeGenRegisterClass *RC :
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Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
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visitRegisterBankClasses(
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RegisterClassHierarchy, RC, "explicit",
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[&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
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DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n");
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Bank.addRegisterClass(RC);
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}, VisitedRCs);
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}
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Banks.push_back(Bank);
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}
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emitSourceFileHeader("Register Bank Source Fragments", OS);
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OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
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<< "#undef GET_REGBANK_DECLARATIONS\n";
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emitHeader(OS, TargetName, Banks);
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OS << "#endif // GET_REGBANK_DECLARATIONS\n\n"
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<< "#ifdef GET_TARGET_REGBANK_CLASS\n"
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<< "#undef GET_TARGET_REGBANK_CLASS\n";
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emitBaseClassDefinition(OS, TargetName, Banks);
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OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"
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<< "#ifdef GET_TARGET_REGBANK_IMPL\n"
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<< "#undef GET_TARGET_REGBANK_IMPL\n";
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emitBaseClassImplementation(OS, TargetName, Banks);
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OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
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}
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namespace llvm {
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void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS) {
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RegisterBankEmitter(RK).run(OS);
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}
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} // end namespace llvm
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