db5ef4fc77
The following systems are involved:
- DB-88F5182
- DB-88F5281
- DB-88F6281
- DB-78100
- SheevaPlug
This overhaul covers the following major changes:
- All integrated peripherals drivers for Marvell ARM SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).
- Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
good by to obio / mbus drivers and numerous hard-coded config data.
Note that world needs to be built WITH_FDT for the affected platforms.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation.
287 lines
9.6 KiB
C
287 lines
9.6 KiB
C
/*-
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* Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MVWIN_H_
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#define _MVWIN_H_
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/*
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* Physical addresses of integrated SoC peripherals
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*/
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#define MV_PHYS_BASE 0xF1000000
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#define MV_SIZE 0x100000
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/*
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* Decode windows addresses (physical)
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*/
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#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE)
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#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE
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#define MV_PCIE_IO_SIZE (1024 * 1024)
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#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE)
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#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
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#define MV_PCI_IO_SIZE (1024 * 1024)
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#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE)
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#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE
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#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024)
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#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE)
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#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
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#define MV_PCI_MEM_SIZE (64 * 1024 * 1024)
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/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */
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/* 512KB NOR FLASH */
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#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE)
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#define MV_DEV_BOOT_SIZE (512 * 1024)
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/* CS0: 7-seg LED */
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#define MV_DEV_CS0_PHYS_BASE 0xFA000000
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#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */
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/* CS1: 32MB NOR FLASH */
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#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE)
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#define MV_DEV_CS1_SIZE (32 * 1024 * 1024)
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/* CS2: 32MB NAND FLASH */
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#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE)
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#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */
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#define MV_CESA_SRAM_PHYS_BASE 0xFD000000
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#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */
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#define MV_CESA_SRAM_SIZE (1024 * 1024)
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/* XXX this is probably not robust against wraparounds... */
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#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF)
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#error Devices memory layout overlaps reset vectors range!
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#endif
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/*
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* Integrated SoC peripherals addresses
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*/
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#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
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#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
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#define MV_MPP_BASE (MV_BASE + 0x10000)
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#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
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#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
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#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
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#define MV_PCI_BASE (MV_BASE + 0x30000)
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#define MV_PCI_SIZE 0x2000
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#define MV_PCIE_BASE (MV_BASE + 0x40000)
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#define MV_PCIE_SIZE 0x2000
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#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
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#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
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#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
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#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
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#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)
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#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000)
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#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
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#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
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#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
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/*
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* Decode windows definitions and macros
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*/
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#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
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#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
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#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
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#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CPU_MAX 14
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#else
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#define MV_WIN_CPU_MAX 8
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#endif
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#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
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#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
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#define MV_WIN_DDR_MAX 4
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00)
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#define MV_WIN_CESA_MAX 4
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CESA_TARGET 9
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#define MV_WIN_CESA_ATTR 1
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#else
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#define MV_WIN_CESA_TARGET 3
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#define MV_WIN_CESA_ATTR 0
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#endif
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#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0)
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#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4)
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#define MV_WIN_USB_MAX 4
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#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
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#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
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#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
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#define MV_WIN_ETH_MAX 6
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#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
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#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
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#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
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#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
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#define MV_WIN_IDMA_MAX 8
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#define MV_IDMA_CHAN_MAX 4
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#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
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#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
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#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
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#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
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#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
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#define MV_WIN_XOR_MAX 8
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#define MV_XOR_CHAN_MAX 2
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#define MV_XOR_NON_REMAP 4
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_PCIE_MEM_TARGET 4
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#define MV_WIN_PCIE_MEM_ATTR 0xE8
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#define MV_WIN_PCIE_IO_TARGET 4
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#define MV_WIN_PCIE_IO_ATTR 0xE0
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#elif defined(SOC_MV_KIRKWOOD)
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#define MV_WIN_PCIE_MEM_TARGET 4
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#define MV_WIN_PCIE_MEM_ATTR 0xE8
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#define MV_WIN_PCIE_IO_TARGET 4
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#define MV_WIN_PCIE_IO_ATTR 0xE0
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#elif defined(SOC_MV_ORION)
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#define MV_WIN_PCIE_MEM_TARGET 4
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#define MV_WIN_PCIE_MEM_ATTR 0x59
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#define MV_WIN_PCIE_IO_TARGET 4
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#define MV_WIN_PCIE_IO_ATTR 0x51
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#define MV_WIN_PCI_MEM_TARGET 3
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#define MV_WIN_PCI_MEM_ATTR 0x59
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#define MV_WIN_PCI_IO_TARGET 3
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#define MV_WIN_PCI_IO_ATTR 0x51
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#endif
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#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x1820)
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#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x1824)
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#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x182C)
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#define MV_WIN_PCIE_MAX 6
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#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804)
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#define MV_PCIE_BAR_MAX 3
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#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
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#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
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#define MV_WIN_SATA_MAX 4
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#define WIN_REG_IDX_RD(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(int i) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
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}
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#define WIN_REG_IDX_RD2(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(int i, int j) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
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} \
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#define WIN_REG_BASE_IDX_RD(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base, int i) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
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}
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#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base, int i, int j) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
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}
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#define WIN_REG_IDX_WR(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(int i, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
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}
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#define WIN_REG_IDX_WR2(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
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}
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#define WIN_REG_BASE_IDX_WR(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
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}
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#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
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}
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#define WIN_REG_RD(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(void) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
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}
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#define WIN_REG_BASE_RD(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
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}
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#define WIN_REG_WR(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off, val); \
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}
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#define WIN_REG_BASE_WR(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off, val); \
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}
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#endif /* _MVWIN_H_ */
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