9cf4fe2ebe
Add ch_suspend/ch_resume methods for PCI controllers and implement them for AHCI. Refactor AHCI channel initialization according to it. Fix Port Multipliers operation. It is far from perfect yet, but works now. Tested with JMicron JMB363 AHCI + SiI 3726 PMP pair. Previous version was also tested with SiI 4726 PMP. Hardware sponsored by: Vitsch Electronics / VEHosting.nl
315 lines
9.9 KiB
C
315 lines
9.9 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_sis_chipinit(device_t dev);
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static int ata_sis_ch_attach(device_t dev);
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static void ata_sis_reset(device_t dev);
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static void ata_sis_setmode(device_t dev, int mode);
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/* misc defines */
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#define SIS_33 1
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#define SIS_66 2
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#define SIS_100NEW 3
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#define SIS_100OLD 4
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#define SIS_133NEW 5
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#define SIS_133OLD 6
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#define SIS_SATA 7
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/*
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* Silicon Integrated Systems Corp. (SiS) chipset support functions
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*/
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static int
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ata_sis_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */
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{ ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */
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{ ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */
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{ ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
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{ ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
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{ ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
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{ ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
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{ ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
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{ ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
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{ ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
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{ ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
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{ ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
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{ ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
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{ ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
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{ ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */
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{ ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */
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{ ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" },
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{ ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" },
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{ ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" },
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{ ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" },
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{ ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" },
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{ 0, 0, 0, 0, 0, 0 }};
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char buffer[64];
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int found = 0;
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if (pci_get_class(dev) != PCIC_STORAGE)
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return (ENXIO);
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if (pci_get_vendor(dev) != ATA_SIS_ID)
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return ENXIO;
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if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
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return ENXIO;
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if (idx->cfg2 && !found) {
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u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
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pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
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if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
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found = 1;
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idx->cfg1 = SIS_133NEW;
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idx->max_dma = ATA_UDMA6;
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sprintf(buffer, "SiS 962/963 %s controller",
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ata_mode2str(idx->max_dma));
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}
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pci_write_config(dev, 0x57, reg57, 1);
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}
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if (idx->cfg2 && !found) {
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u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
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pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
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if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
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struct ata_chip_id id[] =
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{{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
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found = 1;
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if (ata_find_chip(dev, id, pci_get_slot(dev))) {
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idx->cfg1 = SIS_133OLD;
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idx->max_dma = ATA_UDMA6;
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}
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else {
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idx->cfg1 = SIS_100NEW;
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idx->max_dma = ATA_UDMA5;
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}
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sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
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}
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pci_write_config(dev, 0x4a, reg4a, 1);
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}
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if (!found)
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sprintf(buffer,"SiS %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ctlr->chipinit = ata_sis_chipinit;
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return 0;
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}
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static int
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ata_sis_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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switch (ctlr->chip->cfg1) {
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case SIS_33:
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break;
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case SIS_66:
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case SIS_100OLD:
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pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
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break;
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case SIS_100NEW:
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case SIS_133OLD:
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pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
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break;
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case SIS_133NEW:
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pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
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pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
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break;
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case SIS_SATA:
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ctlr->r_type2 = SYS_RES_IOPORT;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE))) {
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ctlr->ch_attach = ata_sis_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->reset = ata_sis_reset;
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}
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ctlr->setmode = ata_sata_setmode;
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return 0;
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default:
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return ENXIO;
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}
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ctlr->setmode = ata_sis_setmode;
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return 0;
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}
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static int
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ata_sis_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return ENXIO;
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
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ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
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ch->r_io[ATA_SERROR].res = ctlr->r_res2;
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ch->r_io[ATA_SERROR].offset = 0x04 + offset;
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
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ch->flags |= ATA_NO_SLAVE;
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/* XXX SOS PHY hotplug handling missing in SiS chip ?? */
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/* XXX SOS unknown how to enable PHY state change interrupt */
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return 0;
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}
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static void
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ata_sis_reset(device_t dev)
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{
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if (ata_sata_phy_reset(dev, -1, 1))
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ata_generic_reset(dev);
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}
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static void
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ata_sis_setmode(device_t dev, int mode)
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{
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device_t gparent = GRANDPARENT(dev);
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struct ata_pci_controller *ctlr = device_get_softc(gparent);
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struct ata_channel *ch = device_get_softc(device_get_parent(dev));
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struct ata_device *atadev = device_get_softc(dev);
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int devno = (ch->unit << 1) + atadev->unit;
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int error;
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mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
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if (ctlr->chip->cfg1 == SIS_133NEW) {
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if (mode > ATA_UDMA2 &&
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pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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}
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else {
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if (mode > ATA_UDMA2 &&
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pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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}
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error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
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if (bootverbose)
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device_printf(dev, "%ssetting %s on %s chip\n",
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(error) ? "FAILURE " : "",
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ata_mode2str(mode), ctlr->chip->text);
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if (!error) {
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switch (ctlr->chip->cfg1) {
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case SIS_133NEW: {
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u_int32_t timings[] =
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{ 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
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0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
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0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
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u_int32_t reg;
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reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
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pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
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break;
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}
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case SIS_133OLD: {
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u_int16_t timings[] =
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{ 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
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0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
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u_int16_t reg = 0x40 + (devno << 1);
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pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
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break;
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}
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case SIS_100NEW: {
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u_int16_t timings[] =
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{ 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
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0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
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u_int16_t reg = 0x40 + (devno << 1);
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pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
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break;
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}
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case SIS_100OLD:
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case SIS_66:
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case SIS_33: {
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u_int16_t timings[] =
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{ 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
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0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
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u_int16_t reg = 0x40 + (devno << 1);
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pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
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break;
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}
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}
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atadev->mode = mode;
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}
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}
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ATA_DECLARE_DRIVER(ata_sis);
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