d212022417
o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
269 lines
6.7 KiB
C
269 lines
6.7 KiB
C
/* $NetBSD: ixp425_timer.c,v 1.11 2006/04/10 03:36:03 simonb Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <arm/xscale/ixp425/ixp425reg.h>
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#include <arm/xscale/ixp425/ixp425var.h>
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static uint32_t counts_per_hz;
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/* callback functions for intr_functions */
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int ixpclk_intr(void *);
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struct ixpclk_softc {
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device_t sc_dev;
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bus_addr_t sc_baseaddr;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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static unsigned ixp425_timer_get_timecount(struct timecounter *tc);
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#ifndef IXP425_CLOCK_FREQ
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#define COUNTS_PER_SEC 66666600 /* 66MHz */
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#else
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#define COUNTS_PER_SEC IXP425_CLOCK_FREQ
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#endif
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#define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1)
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static struct ixpclk_softc *ixpclk_sc = NULL;
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#define GET_TS_VALUE(sc) (*(volatile u_int32_t *) \
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(IXP425_TIMER_VBASE + IXP425_OST_TS))
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static struct timecounter ixp425_timer_timecounter = {
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ixp425_timer_get_timecount, /* get_timecount */
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NULL, /* no poll_pps */
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~0u, /* counter_mask */
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COUNTS_PER_SEC, /* frequency */
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"IXP4XX Timer", /* name */
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1000, /* quality */
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};
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static int
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ixpclk_probe(device_t dev)
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{
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device_set_desc(dev, "IXP4XX Timer");
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return (0);
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}
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static int
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ixpclk_attach(device_t dev)
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{
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struct ixpclk_softc *sc = device_get_softc(dev);
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struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
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ixpclk_sc = sc;
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sc->sc_dev = dev;
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sc->sc_iot = sa->sc_iot;
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sc->sc_baseaddr = IXP425_TIMER_HWBASE;
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if (bus_space_map(sc->sc_iot, sc->sc_baseaddr, 8, 0,
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&sc->sc_ioh))
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panic("%s: Cannot map registers", device_get_name(dev));
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return (0);
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}
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static device_method_t ixpclk_methods[] = {
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DEVMETHOD(device_probe, ixpclk_probe),
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DEVMETHOD(device_attach, ixpclk_attach),
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{0, 0},
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};
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static driver_t ixpclk_driver = {
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"ixpclk",
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ixpclk_methods,
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sizeof(struct ixpclk_softc),
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};
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static devclass_t ixpclk_devclass;
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DRIVER_MODULE(ixpclk, ixp, ixpclk_driver, ixpclk_devclass, 0, 0);
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static unsigned
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ixp425_timer_get_timecount(struct timecounter *tc)
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{
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uint32_t ret;
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ret = GET_TS_VALUE(sc);
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return (ret);
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}
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/*
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* cpu_initclocks:
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*
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* Initialize the clock and get them going.
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*/
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void
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cpu_initclocks(void)
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{
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struct ixpclk_softc* sc = ixpclk_sc;
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struct resource *irq;
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device_t dev = sc->sc_dev;
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u_int oldirqstate;
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int rid = 0;
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void *ihl;
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if (hz < 50 || COUNTS_PER_SEC % hz) {
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printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
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hz = 100;
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}
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tick = 1000000 / hz; /* number of microseconds between interrupts */
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/*
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* We only have one timer available; stathz and profhz are
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* always left as 0 (the upper-layer clock code deals with
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* this situation).
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*/
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if (stathz != 0)
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printf("Cannot get %d Hz statclock\n", stathz);
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stathz = 0;
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if (profhz != 0)
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printf("Cannot get %d Hz profclock\n", profhz);
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profhz = 0;
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/* Report the clock frequency. */
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oldirqstate = disable_interrupts(I32_bit);
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irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0,
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IXP425_INT_TMR0, 1, RF_ACTIVE);
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if (!irq)
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panic("Unable to setup the clock irq handler.\n");
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else
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bus_setup_intr(dev, irq, INTR_TYPE_CLK, ixpclk_intr, NULL,
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NULL, &ihl);
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/* Set up the new clock parameters. */
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/* clear interrupt */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
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OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT |
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OST_TIM1_INT | OST_TIM0_INT);
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counts_per_hz = COUNTS_PER_SEC / hz;
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/* reload value & Timer enable */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD,
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(counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN);
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tc_init(&ixp425_timer_timecounter);
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restore_interrupts(oldirqstate);
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rid = 0;
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}
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/*
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* DELAY:
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*
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* Delay for at least N microseconds.
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*/
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void
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DELAY(int n)
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{
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u_int32_t first, last;
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int usecs;
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if (n == 0)
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return;
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/*
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* Clamp the timeout at a maximum value (about 32 seconds with
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* a 66MHz clock). *Nobody* should be delay()ing for anywhere
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* near that length of time and if they are, they should be hung
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* out to dry.
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*/
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if (n >= (0x80000000U / COUNTS_PER_USEC))
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usecs = (0x80000000U / COUNTS_PER_USEC) - 1;
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else
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usecs = n * COUNTS_PER_USEC;
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/* Note: Timestamp timer counts *up*, unlike the other timers */
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first = GET_TS_VALUE();
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while (usecs > 0) {
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last = GET_TS_VALUE();
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usecs -= (int)(last - first);
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first = last;
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}
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}
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/*
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* ixpclk_intr:
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*
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* Handle the hardclock interrupt.
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*/
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int
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ixpclk_intr(void *arg)
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{
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struct ixpclk_softc* sc = ixpclk_sc;
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struct trapframe *frame = arg;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
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OST_TIM0_INT);
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hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
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return (FILTER_HANDLED);
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}
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void
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cpu_startprofclock(void)
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{
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}
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void
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cpu_stopprofclock(void)
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{
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}
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