d212022417
o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
23 lines
676 B
Plaintext
23 lines
676 B
Plaintext
#$FreeBSD$
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#
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# Gateworks GW23XX board configuration
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#
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files "../xscale/ixp425/files.avila"
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#
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# Physical memory starts at 0. We assume images are loaded at
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# 0x200000, e.g. from redboot with load -b 0x200000 kernel.
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#
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# Redboot is expected to handle unmapping the flash memory that
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# appears at 0 on boot. Likewise we expect the expansion bus to
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# be remapped away from 0.
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#
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options PHYSADDR=0x00000000
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options KERNPHYSADDR=0x00200000
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makeoptions KERNPHYSADDR=0x00200000
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options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
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makeoptions KERNVIRTADDR=0xc0200000
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options FLASHADDR=0x50000000
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options LOADERRAMADDR=0x00000000
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options STARTUP_PAGETABLE_ADDR=0x00000000
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