eeb913c99f
(1) Invoke cpp to bring in files via #include (although the old
/include/ stuff is supported still).
(2) bring in files from either vendor tree or freebsd-custom files
when building.
(3) move all dts* files from sys/boot/fdt/dts to
sys/boot/fdt/dts/${MACHINE} as appropriate.
(4) encode all the magic to do the build in sys/tools/fdt/make_dtb.sh
so that the different places in the tree use the exact same logic.
(5) switch back to gpl dtc by default. the bsdl one in the tree has
significant issues not easily addressed by those unfamiliar with
the code.
584 lines
14 KiB
Plaintext
584 lines
14 KiB
Plaintext
/*
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* P5020DS Device Tree Source
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*
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* Copyright 2010-2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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/include/ "p5020si.dtsi"
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/ {
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model = "fsl,P5020DS";
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compatible = "fsl,P5020DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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phy_rgmii_0 = &phy_rgmii_0;
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phy_rgmii_1 = &phy_rgmii_1;
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phy_sgmii_1c = &phy_sgmii_1c;
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phy_sgmii_1d = &phy_sgmii_1d;
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phy_sgmii_1e = &phy_sgmii_1e;
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phy_sgmii_1f = &phy_sgmii_1f;
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phy_xgmii_1 = &phy_xgmii_1;
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phy_xgmii_2 = &phy_xgmii_2;
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emi1_rgmii = &hydra_mdio_rgmii;
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emi1_sgmii = &hydra_mdio_sgmii;
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emi2_xgmii = &hydra_mdio_xgmii;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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bman-portals@ff4000000 {
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bman-portal@0 {
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cpu-handle = <&cpu0>;
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};
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bman-portal@4000 {
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cpu-handle = <&cpu1>;
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};
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bman-portal@8000 {
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};
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bman-portal@c000 {
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};
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bman-portal@10000 {
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};
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bman-portal@14000 {
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};
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bman-portal@18000 {
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};
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bman-portal@1c000 {
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};
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bman-portal@20000 {
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};
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bman-portal@24000 {
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};
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buffer-pool@0 {
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compatible = "fsl,p5020-bpool", "fsl,bpool";
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fsl,bpid = <0>;
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fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
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};
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};
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qman-portals@ff4200000 {
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qportal0: qman-portal@0 {
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cpu-handle = <&cpu0>;
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal1: qman-portal@4000 {
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cpu-handle = <&cpu1>;
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal2: qman-portal@8000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal3: qman-portal@c000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal4: qman-portal@10000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal5: qman-portal@14000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal6: qman-portal@18000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal7: qman-portal@1c000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal8: qman-portal@20000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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qportal9: qman-portal@24000 {
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fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
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&qpool4 &qpool5 &qpool6
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&qpool7 &qpool8 &qpool9
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&qpool10 &qpool11 &qpool12
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&qpool13 &qpool14 &qpool15>;
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};
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};
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soc: soc@ffe000000 {
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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i2c@118100 {
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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};
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i2c@119100 {
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
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};
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pme: pme@316000 {
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/* Commented out, use default allocation */
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/* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
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/* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
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};
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qman: qman@318000 {
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/* Commented out, use default allocation */
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/* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
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/* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
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};
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bman: bman@31a000 {
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/* Same as fsl,qman-*, use default allocation */
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/* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
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};
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fman0: fman@400000 {
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enet0: ethernet@e0000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy_rgmii_0>;
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phy-connection-type = "rgmii";
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};
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mdio0: mdio@e1120 {
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tbi0: tbi-phy@8 {
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reg = <0x8>;
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|
device_type = "tbi-phy";
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|
};
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/*
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* Virtual MDIO for the two on-board RGMII
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* ports. The fsl,hydra-mdio-muxval property
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* is already correct.
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*/
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hydra_mdio_rgmii: hydra-mdio-rgmii {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,hydra-mdio";
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fsl,mdio-handle = <&mdio0>;
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fsl,hydra-mdio-muxval = <0x00>;
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status = "disabled";
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|
phy_rgmii_0: ethernet-phy@0 {
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reg = <0x0>;
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|
};
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phy_rgmii_1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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/*
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* Virtual MDIO for the four-port SGMII card.
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* The fsl,hydra-mdio-muxval property will be
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* fixed-up by U-Boot based on the slot that
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* the SGMII card is in.
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*
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* Note: we do not support DTSEC5 connected to
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* SGMII, so this is the only SGMII node.
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*/
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hydra_mdio_sgmii: hydra-mdio-sgmii {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,hydra-mdio";
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fsl,mdio-handle = <&mdio0>;
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fsl,hydra-mdio-muxval = <0x00>;
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status = "disabled";
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|
phy_sgmii_1c: ethernet-phy@1c {
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reg = <0x1c>;
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|
};
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|
phy_sgmii_1d: ethernet-phy@1d {
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|
reg = <0x1d>;
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|
};
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|
phy_sgmii_1e: ethernet-phy@1e {
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|
reg = <0x1e>;
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|
};
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|
phy_sgmii_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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enet1: ethernet@e2000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy_sgmii_1d>;
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phy-connection-type = "sgmii";
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};
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mdio@e3120 {
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tbi1: tbi-phy@8 {
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reg = <8>;
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device_type = "tbi-phy";
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};
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};
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|
enet2: ethernet@e4000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy_sgmii_1e>;
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phy-connection-type = "sgmii";
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|
};
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|
mdio@e5120 {
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tbi2: tbi-phy@8 {
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reg = <8>;
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|
device_type = "tbi-phy";
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|
};
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};
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|
enet3: ethernet@e6000 {
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tbi-handle = <&tbi3>;
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|
phy-handle = <&phy_sgmii_1f>;
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phy-connection-type = "sgmii";
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|
};
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|
mdio@e7120 {
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#address-cells = <1>;
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|
#size-cells = <0>;
|
|
compatible = "fsl,fman-tbi";
|
|
reg = <0xe7120 0xee0>;
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|
interrupts = <100 1 0 0>;
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|
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|
tbi3: tbi-phy@8 {
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|
reg = <8>;
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|
device_type = "tbi-phy";
|
|
};
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|
};
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|
enet4: ethernet@e8000 {
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tbi-handle = <&tbi4>;
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|
phy-handle = <&phy_rgmii_1>;
|
|
phy-connection-type = "rgmii";
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|
};
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|
mdio@e9120 {
|
|
tbi4: tbi-phy@8 {
|
|
reg = <8>;
|
|
device_type = "tbi-phy";
|
|
};
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};
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|
enet5: ethernet@f0000 {
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/*
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* phy-handle will be updated by U-Boot to
|
|
* reflect the actual slot the XAUI card is in.
|
|
*/
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phy-handle = <&phy_xgmii_1>;
|
|
phy-connection-type = "xgmii";
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|
};
|
|
|
|
/*
|
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* We only support one XAUI card, so the MDIO muxing
|
|
* is set by U-Boot, and Linux never touches it.
|
|
* Therefore, we don't need a virtual MDIO node.
|
|
* However, the phy address depends on the slot, so
|
|
* only one of the ethernet-phy nodes below will be
|
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* used.
|
|
*/
|
|
hydra_mdio_xgmii: mdio@f1000 {
|
|
status = "disabled";
|
|
|
|
/* XAUI card in slot 1 */
|
|
phy_xgmii_1: ethernet-phy@4 {
|
|
reg = <0x4>;
|
|
};
|
|
|
|
/* XAUI card in slot 2 */
|
|
phy_xgmii_2: ethernet-phy@0 {
|
|
reg = <0x0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rapidio@ffe0c0000 {
|
|
reg = <0xf 0xfe0c0000 0 0x11000>;
|
|
|
|
port1 {
|
|
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
|
};
|
|
port2 {
|
|
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
|
};
|
|
};
|
|
|
|
localbus@ffe124000 {
|
|
reg = <0xf 0xfe124000 0 0x1000>;
|
|
ranges = <0 0 0xf 0xb8000000 0x04000000>;
|
|
|
|
flash@0,0 {
|
|
compatible = "cfi-flash";
|
|
/*
|
|
* Map 64Mb of 128MB NOR flash memory. Since highest
|
|
* line of address of NOR flash memory are set by
|
|
* FPGA, memory are divided into two pages equal to
|
|
* 64MB. One of the pages can be accessed at once.
|
|
*/
|
|
reg = <0 0 0x04000000>;
|
|
bank-width = <2>;
|
|
device-width = <2>;
|
|
};
|
|
|
|
nand@2,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,elbc-fcm-nand";
|
|
reg = <0x2 0x0 0x40000>;
|
|
|
|
partition@0 {
|
|
label = "NAND U-Boot Image";
|
|
reg = <0x0 0x02000000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@2000000 {
|
|
label = "NAND Root File System";
|
|
reg = <0x02000000 0x10000000>;
|
|
};
|
|
|
|
partition@12000000 {
|
|
label = "NAND Compressed RFS Image";
|
|
reg = <0x12000000 0x08000000>;
|
|
};
|
|
|
|
partition@1a000000 {
|
|
label = "NAND Linux Kernel Image";
|
|
reg = <0x1a000000 0x04000000>;
|
|
};
|
|
|
|
partition@1e000000 {
|
|
label = "NAND DTB Image";
|
|
reg = <0x1e000000 0x01000000>;
|
|
};
|
|
|
|
partition@1f000000 {
|
|
label = "NAND Writable User area";
|
|
reg = <0x1f000000 0x21000000>;
|
|
};
|
|
};
|
|
|
|
board-control@3,0 {
|
|
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
|
|
reg = <3 0 0x30>;
|
|
};
|
|
};
|
|
|
|
pci0: pcie@ffe200000 {
|
|
reg = <0xf 0xfe200000 0 0x1000>;
|
|
ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
|
|
0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0x80000000
|
|
0x02000000 0 0x80000000
|
|
0 0x10000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0xff000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci1: pcie@ffe201000 {
|
|
reg = <0xf 0xfe201000 0 0x1000>;
|
|
ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
|
|
0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0x90000000
|
|
0x02000000 0 0x90000000
|
|
0 0x10000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0xff010000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci2: pcie@ffe202000 {
|
|
reg = <0xf 0xfe202000 0 0x1000>;
|
|
ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xa0000000
|
|
0x02000000 0 0xa0000000
|
|
0 0x10000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0xff020000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci3: pcie@ffe203000 {
|
|
reg = <0xf 0xfe203000 0 0x1000>;
|
|
ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
|
|
0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xb0000000
|
|
0x02000000 0 0xb0000000
|
|
0 0x08000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0xff030000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
fsl,dpaa {
|
|
compatible = "fsl,p5020-dpaa", "fsl,dpaa";
|
|
|
|
ethernet@0 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet0>;
|
|
status = "okay";
|
|
};
|
|
ethernet@1 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet1>;
|
|
status = "disabled";
|
|
};
|
|
ethernet@2 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet2>;
|
|
status = "disabled";
|
|
};
|
|
ethernet@3 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet3>;
|
|
status = "disabled";
|
|
};
|
|
ethernet@4 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet4>;
|
|
status = "okay";
|
|
};
|
|
ethernet@5 {
|
|
compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
|
|
fsl,qman-channel = <&qpool1>;
|
|
fsl,fman-mac = <&enet5>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
stdin = "serial0";
|
|
stdout = "serial0";
|
|
};
|
|
};
|