dbdfe960cb
main component in the southbridge chip to determine which VIA chip we are dealing with. Try to enable DMA on generic controllers that say they has the capability, instead of relying on the BIOS to have set it up.
200 lines
7.5 KiB
C
200 lines
7.5 KiB
C
/*-
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* Copyright (c) 1998,1999 Søren Schmidt
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* ATA register defines */
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#define ATA_DATA 0x00 /* data register */
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#define ATA_ERROR 0x01 /* (R) error register */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_FEATURE 0x01 /* (W) feature register */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 0x02 /* (W) sector count */
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#define ATA_IREASON 0x02 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_SECTOR 0x03 /* sector # */
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#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
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#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
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#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
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#define ATA_D_LBA 0x40 /* use LBA adressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_CMD 0x07 /* command register */
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#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
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#define ATA_C_READ 0x20 /* read command */
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#define ATA_C_WRITE 0x30 /* write command */
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#define ATA_C_PACKET_CMD 0xa0 /* packet command */
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#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
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#define ATA_C_READ_MULTI 0xc4 /* read multi command */
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#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
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#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
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#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
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#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
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#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
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#define ATA_C_SETFEATURES 0xef /* features command */
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#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
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#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
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#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
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#define ATA_STATUS 0x07 /* status register */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_ALTPORT 0x206 /* alternate Status register */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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/* misc defines */
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#define ATA_MASTER 0x00
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#define ATA_SLAVE 0x10
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#define ATA_IOSIZE 0x08
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#define ATA_OP_FINISHED 0x00
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#define ATA_OP_CONTINUES 0x01
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/* busmaster DMA related defines */
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#define ATA_BM_OFFSET1 0x08
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#define ATA_DMA_ENTRIES 256
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#define ATA_DMA_EOT 0x80000000
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#define ATA_BMCMD_PORT 0x00
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#define ATA_BMCMD_START_STOP 0x01
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#define ATA_BMCMD_WRITE_READ 0x08
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#define ATA_BMSTAT_PORT 0x02
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#define ATA_BMSTAT_ACTIVE 0x01
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#define ATA_BMSTAT_ERROR 0x02
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#define ATA_BMSTAT_INTERRUPT 0x04
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#define ATA_BMSTAT_MASK 0x07
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#define ATA_BMSTAT_DMA_MASTER 0x20
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#define ATA_BMSTAT_DMA_SLAVE 0x40
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#define ATA_BMSTAT_DMA_SIMPLEX 0x80
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#define ATA_BMDTP_PORT 0x04
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/* structure for holding DMA address data */
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struct ata_dmaentry {
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u_int32_t base;
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u_int32_t count;
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};
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/* ATA device DMA access modes */
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#define ATA_WDMA2 0x22
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#define ATA_UDMA2 0x42
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#define ATA_UDMA3 0x43
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#define ATA_UDMA4 0x44
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/* structure describing an ATA device */
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struct ata_softc {
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int32_t unit; /* unit on this controller */
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int32_t lun; /* logical unit # */
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struct device *dev; /* device handle */
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int32_t ioaddr; /* port addr */
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int32_t altioaddr; /* alternate port addr */
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int32_t bmaddr; /* bus master DMA port */
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void *dev_softc[2]; /* ptr to devices softc's */
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struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
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int32_t mode[2]; /* transfer mode for devices */
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#define ATA_MODE_PIO 0x00
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#define ATA_MODE_WDMA2 0x01
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#define ATA_MODE_UDMA2 0x02
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#define ATA_MODE_UDMA3 0x04
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#define ATA_MODE_UDMA4 0x08
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int32_t flags; /* controller flags */
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#define ATA_DMA_ACTIVE 0x01
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#define ATA_ATAPI_DMA_RO 0x02
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int32_t devices; /* what is present */
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#define ATA_ATA_MASTER 0x01
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#define ATA_ATA_SLAVE 0x02
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#define ATA_ATAPI_MASTER 0x04
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#define ATA_ATAPI_SLAVE 0x08
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u_int8_t status; /* last controller status */
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u_int8_t error; /* last controller error */
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int32_t active; /* active processing request */
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#define ATA_IDLE 0x0
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#define ATA_IMMEDIATE 0x0
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#define ATA_WAIT_INTR 0x1
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#define ATA_WAIT_READY 0x2
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#define ATA_ACTIVE_ATA 0x3
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#define ATA_ACTIVE_ATAPI 0x4
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#define ATA_REINITING 0x5
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TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
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TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
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void *running; /* currently running request */
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#if NAPM > 0
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struct apmhook resume_hook; /* hook for apm */
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#endif
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};
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/* array to hold all ata softc's */
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extern struct ata_softc *atadevices[];
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#define MAXATA 16
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/* public prototypes */
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void ata_start(struct ata_softc *);
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void ata_reset(struct ata_softc *, int32_t *);
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int32_t ata_reinit(struct ata_softc *);
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int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
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int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
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int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
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int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
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void ata_dmastart(struct ata_softc *);
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int32_t ata_dmastatus(struct ata_softc *);
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int32_t ata_dmadone(struct ata_softc *);
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int8_t *ata_mode2str(int32_t);
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void bswap(int8_t *, int32_t);
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void btrim(int8_t *, int32_t);
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void bpack(int8_t *, int8_t *, int32_t);
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int32_t ata_find_dev(device_t, int32_t);
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