49e368ac48
When using DW UART with BUSY detection it is necessary to wait until all serial transfers are finished before manipulating the line control. LCR will not be affected when UART is busy. In addition, if Divisor Latch Access Bit is being set in order to modify UART divisors: 1. We will get BUSY interrupt if interrupts are enabled. 2. Because LCR will not be affected the THR and (even worse) IER contents will be corrupted. This will lead to console hang. Approved by: cognet (mentor)
925 lines
22 KiB
C
925 lines
22 KiB
C
/*-
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_dev_ns8250.h>
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#include <dev/ic/ns16550.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK 1843200
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static int broken_txfifo = 0;
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SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
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&broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
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TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
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/*
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* Clear pending interrupts. THRE is cleared by reading IIR. Data
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* that may have been received gets lost here.
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*/
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static void
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ns8250_clrint(struct uart_bas *bas)
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{
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uint8_t iir, lsr;
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iir = uart_getreg(bas, REG_IIR);
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while ((iir & IIR_NOPEND) == 0) {
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iir &= IIR_IMASK;
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if (iir == IIR_RLS) {
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lsr = uart_getreg(bas, REG_LSR);
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if (lsr & (LSR_BI|LSR_FE|LSR_PE))
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(void)uart_getreg(bas, REG_DATA);
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} else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
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(void)uart_getreg(bas, REG_DATA);
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else if (iir == IIR_MLSC)
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(void)uart_getreg(bas, REG_MSR);
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uart_barrier(bas);
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iir = uart_getreg(bas, REG_IIR);
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}
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}
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static int
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ns8250_delay(struct uart_bas *bas)
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{
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int divisor;
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u_char lcr;
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lcr = uart_getreg(bas, REG_LCR);
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uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
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uart_barrier(bas);
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divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
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uart_barrier(bas);
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uart_setreg(bas, REG_LCR, lcr);
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uart_barrier(bas);
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/* 1/10th the time to transmit 1 character (estimate). */
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if (divisor <= 134)
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return (16000000 * divisor / bas->rclk);
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return (16000 * divisor / (bas->rclk / 1000));
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}
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static int
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ns8250_divisor(int rclk, int baudrate)
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{
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int actual_baud, divisor;
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int error;
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if (baudrate == 0)
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return (0);
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divisor = (rclk / (baudrate << 3) + 1) >> 1;
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if (divisor == 0 || divisor >= 65536)
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return (0);
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actual_baud = rclk / (divisor << 4);
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/* 10 times error in percent: */
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error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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return (0);
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return (divisor);
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}
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static int
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ns8250_drain(struct uart_bas *bas, int what)
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{
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int delay, limit;
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delay = ns8250_delay(bas);
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if (what & UART_DRAIN_TRANSMITTER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs.
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*/
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limit = 10*1024;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(delay);
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if (limit == 0) {
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/* printf("ns8250: transmitter appears stuck... "); */
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return (EIO);
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}
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}
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if (what & UART_DRAIN_RECEIVER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs and integrated
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* UARTs. The HP rx2600 for example has 3 UARTs on the
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* management board that tend to get a lot of data send
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* to it when the UART is first activated.
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*/
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limit=10*4096;
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
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(void)uart_getreg(bas, REG_DATA);
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uart_barrier(bas);
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DELAY(delay << 2);
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}
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if (limit == 0) {
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/* printf("ns8250: receiver appears broken... "); */
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return (EIO);
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}
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}
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return (0);
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}
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/*
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* We can only flush UARTs with FIFOs. UARTs without FIFOs should be
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* drained. WARNING: this function clobbers the FIFO setting!
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*/
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static void
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ns8250_flush(struct uart_bas *bas, int what)
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{
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uint8_t fcr;
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fcr = FCR_ENABLE;
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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fcr |= FCR_RCV_RST;
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uart_setreg(bas, REG_FCR, fcr);
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uart_barrier(bas);
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}
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static int
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ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int divisor;
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uint8_t lcr;
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lcr = 0;
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if (databits >= 8)
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lcr |= LCR_8BITS;
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else if (databits == 7)
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lcr |= LCR_7BITS;
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else if (databits == 6)
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lcr |= LCR_6BITS;
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else
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lcr |= LCR_5BITS;
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if (stopbits > 1)
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lcr |= LCR_STOPB;
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lcr |= parity << 3;
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/* Set baudrate. */
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if (baudrate > 0) {
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divisor = ns8250_divisor(bas->rclk, baudrate);
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if (divisor == 0)
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return (EINVAL);
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uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
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uart_barrier(bas);
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uart_setreg(bas, REG_DLL, divisor & 0xff);
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uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
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uart_barrier(bas);
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}
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/* Set LCR and clear DLAB. */
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uart_setreg(bas, REG_LCR, lcr);
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int ns8250_probe(struct uart_bas *bas);
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static void ns8250_init(struct uart_bas *bas, int, int, int, int);
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static void ns8250_term(struct uart_bas *bas);
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static void ns8250_putc(struct uart_bas *bas, int);
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static int ns8250_rxready(struct uart_bas *bas);
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static int ns8250_getc(struct uart_bas *bas, struct mtx *);
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struct uart_ops uart_ns8250_ops = {
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.probe = ns8250_probe,
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.init = ns8250_init,
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.term = ns8250_term,
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.putc = ns8250_putc,
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.rxready = ns8250_rxready,
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.getc = ns8250_getc,
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};
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static int
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ns8250_probe(struct uart_bas *bas)
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{
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u_char val;
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/* Check known 0 bits that don't depend on DLAB. */
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val = uart_getreg(bas, REG_IIR);
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if (val & 0x30)
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return (ENXIO);
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/*
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* Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
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* chip, but otherwise doesn't seem to have a function. In
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* other words, uart(4) works regardless. Ignore that bit so
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* the probe succeeds.
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*/
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val = uart_getreg(bas, REG_MCR);
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if (val & 0xa0)
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return (ENXIO);
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return (0);
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}
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static void
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ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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u_char ier;
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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ns8250_param(bas, baudrate, databits, stopbits, parity);
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/* Disable all interrupt sources. */
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/*
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* We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
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* UARTs split the receive time-out interrupt bit out separately as
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* 0x10. This gets handled by ier_mask and ier_rxbits below.
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*/
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ier = uart_getreg(bas, REG_IER) & 0xe0;
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uart_setreg(bas, REG_IER, ier);
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uart_barrier(bas);
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/* Disable the FIFO (if present). */
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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/* Set RTS & DTR. */
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uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
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uart_barrier(bas);
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ns8250_clrint(bas);
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}
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static void
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ns8250_term(struct uart_bas *bas)
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{
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/* Clear RTS & DTR. */
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uart_setreg(bas, REG_MCR, MCR_IE);
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uart_barrier(bas);
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}
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static void
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ns8250_putc(struct uart_bas *bas, int c)
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{
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int limit;
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
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DELAY(4);
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uart_setreg(bas, REG_DATA, c);
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uart_barrier(bas);
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(4);
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}
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static int
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ns8250_rxready(struct uart_bas *bas)
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{
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return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
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}
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static int
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ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
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uart_unlock(hwmtx);
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DELAY(4);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, REG_DATA);
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uart_unlock(hwmtx);
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return (c);
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}
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static kobj_method_t ns8250_methods[] = {
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KOBJMETHOD(uart_attach, ns8250_bus_attach),
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KOBJMETHOD(uart_detach, ns8250_bus_detach),
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KOBJMETHOD(uart_flush, ns8250_bus_flush),
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KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
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KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
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KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
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KOBJMETHOD(uart_param, ns8250_bus_param),
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KOBJMETHOD(uart_probe, ns8250_bus_probe),
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KOBJMETHOD(uart_receive, ns8250_bus_receive),
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KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
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KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_ns8250_class = {
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"ns8250",
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ns8250_methods,
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sizeof(struct ns8250_softc),
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.uc_ops = &uart_ns8250_ops,
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.uc_range = 8,
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.uc_rclk = DEFAULT_RCLK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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int
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ns8250_bus_attach(struct uart_softc *sc)
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{
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struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
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struct uart_bas *bas;
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unsigned int ivar;
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#ifdef FDT
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phandle_t node;
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pcell_t cell;
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#endif
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ns8250->busy_detect = 0;
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#ifdef FDT
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/*
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* Check whether uart requires to read USR reg when IIR_BUSY and
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* has broken txfifo.
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*/
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node = ofw_bus_get_node(sc->sc_dev);
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if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
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ns8250->busy_detect = 1;
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if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
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broken_txfifo = 1;
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#endif
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bas = &sc->sc_bas;
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ns8250->mcr = uart_getreg(bas, REG_MCR);
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ns8250->fcr = FCR_ENABLE;
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if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
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&ivar)) {
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if (UART_FLAGS_FCR_RX_LOW(ivar))
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ns8250->fcr |= FCR_RX_LOW;
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else if (UART_FLAGS_FCR_RX_MEDL(ivar))
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ns8250->fcr |= FCR_RX_MEDL;
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else if (UART_FLAGS_FCR_RX_HIGH(ivar))
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ns8250->fcr |= FCR_RX_HIGH;
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else
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ns8250->fcr |= FCR_RX_MEDH;
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} else
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ns8250->fcr |= FCR_RX_MEDH;
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/* Get IER mask */
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ivar = 0xf0;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
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&ivar);
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ns8250->ier_mask = (uint8_t)(ivar & 0xff);
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/* Get IER RX interrupt bits */
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ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
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&ivar);
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ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
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uart_setreg(bas, REG_FCR, ns8250->fcr);
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uart_barrier(bas);
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ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
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if (ns8250->mcr & MCR_DTR)
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sc->sc_hwsig |= SER_DTR;
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if (ns8250->mcr & MCR_RTS)
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sc->sc_hwsig |= SER_RTS;
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ns8250_bus_getsig(sc);
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ns8250_clrint(bas);
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ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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ns8250->ier |= ns8250->ier_rxbits;
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uart_setreg(bas, REG_IER, ns8250->ier);
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uart_barrier(bas);
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/*
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* Timing of the H/W access was changed with r253161 of uart_core.c
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* It has been observed that an ITE IT8513E would signal a break
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* condition with pretty much every character it received, unless
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* it had enough time to settle between ns8250_bus_attach() and
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* ns8250_bus_ipend() -- which it accidentally had before r253161.
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* It's not understood why the UART chip behaves this way and it
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* could very well be that the DELAY make the H/W work in the same
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* accidental manner as before. More analysis is warranted, but
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* at least now we fixed a known regression.
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*/
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DELAY(200);
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return (0);
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}
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int
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ns8250_bus_detach(struct uart_softc *sc)
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{
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struct ns8250_softc *ns8250;
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struct uart_bas *bas;
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u_char ier;
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ns8250 = (struct ns8250_softc *)sc;
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bas = &sc->sc_bas;
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ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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uart_setreg(bas, REG_IER, ier);
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uart_barrier(bas);
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ns8250_clrint(bas);
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return (0);
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}
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int
|
|
ns8250_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
if (sc->sc_rxfifosz > 1) {
|
|
ns8250_flush(bas, what);
|
|
uart_setreg(bas, REG_FCR, ns8250->fcr);
|
|
uart_barrier(bas);
|
|
error = 0;
|
|
} else
|
|
error = ns8250_drain(bas, what);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
uint32_t new, old, sig;
|
|
uint8_t msr;
|
|
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
sig = old;
|
|
uart_lock(sc->sc_hwmtx);
|
|
msr = uart_getreg(&sc->sc_bas, REG_MSR);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
|
|
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
|
|
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
|
|
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
|
|
new = sig & ~SER_MASK_DELTA;
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
return (sig);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
struct uart_bas *bas;
|
|
int baudrate, divisor, error;
|
|
uint8_t efr, lcr;
|
|
|
|
bas = &sc->sc_bas;
|
|
error = 0;
|
|
uart_lock(sc->sc_hwmtx);
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
if (data)
|
|
lcr |= LCR_SBREAK;
|
|
else
|
|
lcr &= ~LCR_SBREAK;
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_IFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_RTS;
|
|
else
|
|
efr &= ~EFR_RTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_OFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_CTS;
|
|
else
|
|
efr &= ~EFR_CTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_BAUD:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
|
|
uart_barrier(bas);
|
|
divisor = uart_getreg(bas, REG_DLL) |
|
|
(uart_getreg(bas, REG_DLH) << 8);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
|
|
if (baudrate > 0)
|
|
*(int*)data = baudrate;
|
|
else
|
|
error = ENXIO;
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
struct ns8250_softc *ns8250;
|
|
int ipend;
|
|
uint8_t iir, lsr;
|
|
|
|
ns8250 = (struct ns8250_softc *)sc;
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
iir = uart_getreg(bas, REG_IIR);
|
|
|
|
if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
|
|
(void)uart_getreg(bas, DW_REG_USR);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
if (iir & IIR_NOPEND) {
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
ipend = 0;
|
|
if (iir & IIR_RXRDY) {
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
if (lsr & LSR_OE)
|
|
ipend |= SER_INT_OVERRUN;
|
|
if (lsr & LSR_BI)
|
|
ipend |= SER_INT_BREAK;
|
|
if (lsr & LSR_RXRDY)
|
|
ipend |= SER_INT_RXREADY;
|
|
} else {
|
|
if (iir & IIR_TXRDY) {
|
|
ipend |= SER_INT_TXIDLE;
|
|
uart_setreg(bas, REG_IER, ns8250->ier);
|
|
} else
|
|
ipend |= SER_INT_SIGCHG;
|
|
}
|
|
if (ipend == 0)
|
|
ns8250_clrint(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (ipend);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
struct ns8250_softc *ns8250;
|
|
struct uart_bas *bas;
|
|
int error, limit;
|
|
|
|
ns8250 = (struct ns8250_softc*)sc;
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
/*
|
|
* When using DW UART with BUSY detection it is necessary to wait
|
|
* until all serial transfers are finished before manipulating the
|
|
* line control. LCR will not be affected when UART is busy.
|
|
*/
|
|
if (ns8250->busy_detect != 0) {
|
|
/*
|
|
* Pick an arbitrary high limit to avoid getting stuck in
|
|
* an infinite loop in case when the hardware is broken.
|
|
*/
|
|
limit = 10 * 1024;
|
|
while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
|
|
--limit)
|
|
DELAY(4);
|
|
|
|
if (limit <= 0) {
|
|
/* UART appears to be stuck */
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (EIO);
|
|
}
|
|
}
|
|
|
|
error = ns8250_param(bas, baudrate, databits, stopbits, parity);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_probe(struct uart_softc *sc)
|
|
{
|
|
struct ns8250_softc *ns8250;
|
|
struct uart_bas *bas;
|
|
int count, delay, error, limit;
|
|
uint8_t lsr, mcr, ier;
|
|
|
|
ns8250 = (struct ns8250_softc *)sc;
|
|
bas = &sc->sc_bas;
|
|
|
|
error = ns8250_probe(bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
mcr = MCR_IE;
|
|
if (sc->sc_sysdev == NULL) {
|
|
/* By using ns8250_init() we also set DTR and RTS. */
|
|
ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
|
|
} else
|
|
mcr |= MCR_DTR | MCR_RTS;
|
|
|
|
error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
|
|
if (error)
|
|
return (error);
|
|
|
|
/*
|
|
* Set loopback mode. This avoids having garbage on the wire and
|
|
* also allows us send and receive data. We set DTR and RTS to
|
|
* avoid the possibility that automatic flow-control prevents
|
|
* any data from being sent.
|
|
*/
|
|
uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
|
|
uart_barrier(bas);
|
|
|
|
/*
|
|
* Enable FIFOs. And check that the UART has them. If not, we're
|
|
* done. Since this is the first time we enable the FIFOs, we reset
|
|
* them.
|
|
*/
|
|
uart_setreg(bas, REG_FCR, FCR_ENABLE);
|
|
uart_barrier(bas);
|
|
if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
|
|
/*
|
|
* NS16450 or INS8250. We don't bother to differentiate
|
|
* between them. They're too old to be interesting.
|
|
*/
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_barrier(bas);
|
|
sc->sc_rxfifosz = sc->sc_txfifosz = 1;
|
|
device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
|
|
return (0);
|
|
}
|
|
|
|
uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
|
|
uart_barrier(bas);
|
|
|
|
count = 0;
|
|
delay = ns8250_delay(bas);
|
|
|
|
/* We have FIFOs. Drain the transmitter and receiver. */
|
|
error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
|
|
if (error) {
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_setreg(bas, REG_FCR, 0);
|
|
uart_barrier(bas);
|
|
goto describe;
|
|
}
|
|
|
|
/*
|
|
* We should have a sufficiently clean "pipe" to determine the
|
|
* size of the FIFOs. We send as much characters as is reasonable
|
|
* and wait for the overflow bit in the LSR register to be
|
|
* asserted, counting the characters as we send them. Based on
|
|
* that count we know the FIFO size.
|
|
*/
|
|
do {
|
|
uart_setreg(bas, REG_DATA, 0);
|
|
uart_barrier(bas);
|
|
count++;
|
|
|
|
limit = 30;
|
|
lsr = 0;
|
|
/*
|
|
* LSR bits are cleared upon read, so we must accumulate
|
|
* them to be able to test LSR_OE below.
|
|
*/
|
|
while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
|
|
--limit)
|
|
DELAY(delay);
|
|
if (limit == 0) {
|
|
ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
|
|
uart_setreg(bas, REG_IER, ier);
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_setreg(bas, REG_FCR, 0);
|
|
uart_barrier(bas);
|
|
count = 0;
|
|
goto describe;
|
|
}
|
|
} while ((lsr & LSR_OE) == 0 && count < 130);
|
|
count--;
|
|
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
|
|
/* Reset FIFOs. */
|
|
ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
describe:
|
|
if (count >= 14 && count <= 16) {
|
|
sc->sc_rxfifosz = 16;
|
|
device_set_desc(sc->sc_dev, "16550 or compatible");
|
|
} else if (count >= 28 && count <= 32) {
|
|
sc->sc_rxfifosz = 32;
|
|
device_set_desc(sc->sc_dev, "16650 or compatible");
|
|
} else if (count >= 56 && count <= 64) {
|
|
sc->sc_rxfifosz = 64;
|
|
device_set_desc(sc->sc_dev, "16750 or compatible");
|
|
} else if (count >= 112 && count <= 128) {
|
|
sc->sc_rxfifosz = 128;
|
|
device_set_desc(sc->sc_dev, "16950 or compatible");
|
|
} else {
|
|
sc->sc_rxfifosz = 16;
|
|
device_set_desc(sc->sc_dev,
|
|
"Non-standard ns8250 class UART with FIFOs");
|
|
}
|
|
|
|
/*
|
|
* Force the Tx FIFO size to 16 bytes for now. We don't program the
|
|
* Tx trigger. Also, we assume that all data has been sent when the
|
|
* interrupt happens.
|
|
*/
|
|
sc->sc_txfifosz = 16;
|
|
|
|
#if 0
|
|
/*
|
|
* XXX there are some issues related to hardware flow control and
|
|
* it's likely that uart(4) is the cause. This basicly needs more
|
|
* investigation, but we avoid using for hardware flow control
|
|
* until then.
|
|
*/
|
|
/* 16650s or higher have automatic flow control. */
|
|
if (sc->sc_rxfifosz > 16) {
|
|
sc->sc_hwiflow = 1;
|
|
sc->sc_hwoflow = 1;
|
|
}
|
|
#endif
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int xc;
|
|
uint8_t lsr;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
while (lsr & LSR_RXRDY) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = uart_getreg(bas, REG_DATA);
|
|
if (lsr & LSR_FE)
|
|
xc |= UART_STAT_FRAMERR;
|
|
if (lsr & LSR_PE)
|
|
xc |= UART_STAT_PARERR;
|
|
uart_rx_put(sc, xc);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
/* Discard everything left in the Rx FIFO. */
|
|
while (lsr & LSR_RXRDY) {
|
|
(void)uart_getreg(bas, REG_DATA);
|
|
uart_barrier(bas);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
uart_lock(sc->sc_hwmtx);
|
|
ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
|
|
if (new & SER_DTR)
|
|
ns8250->mcr |= MCR_DTR;
|
|
if (new & SER_RTS)
|
|
ns8250->mcr |= MCR_RTS;
|
|
uart_setreg(bas, REG_MCR, ns8250->mcr);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
ns8250_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int i;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
|
|
;
|
|
uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
|
|
uart_barrier(bas);
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
|
|
uart_barrier(bas);
|
|
}
|
|
if (broken_txfifo)
|
|
ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
|
|
else
|
|
sc->sc_txbusy = 1;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
if (broken_txfifo)
|
|
uart_sched_softih(sc, SER_INT_TXIDLE);
|
|
return (0);
|
|
}
|