dd1290f033
Filter incoming transfer negotiation requests to ensure they never exceed the settings specified by the user. In restart sequencer attempt to deal with a bug in the aic7895. If a third party reset occurs at just the right time, the stack register can lock up. When restarting the sequencer after handling the SCSI reset, poke SEQADDR1 before resting the sequencers program counter. When something strange happens, dump the card's transaction state via ahc_dump_card_state(). This should aid in debugging. Handle request sense transactions via the QINFIFO instead of attaching them to the waiting queue directly. The waiting queue consumes card SCB resources and, in the pathological case of every target on the bus beating our selection attemps and issuing a check condition, could have caused us to run out of SCBs. I have never seen this happen, and only early cards with 3 or 4 SCBs had any real chance of ever getting into this state. Add additional sequencer interrupt codes to support firmware diagnostics. The diagnostic code is enabled with the AHC_DEBUG_SEQUENCER kernel option. Make it possible to switch into and out of target mode on the fly. The card comes up by default as an initiator but will switch into target mode as soon as an enable lun operation is performed. As always, target mode behavior is gated by the AHC_TMODE_ENABLE kernel option so most users will not be affected by this change. In ahc_update_target_msg_request(), also issue a new request if the ppr_options have changed. Never issue a PPR as a target. It is forbidden by the spec. Correct a bug in ahc_parse_msg() that prevented us from responding to PPR messages as a target. Mark SCBs that are on the untagged queue with a flag instead of checking several fields in the SCB to see if the SCB should be on the queue. This makes it easier for things like automatic request sense requests to be queued without touching the untagged queues even though they are untagged requests. When dealing with ignore wide residue messages that occur in the middle of a transfer, reset HADDR, not SHADDR for non-ultra2 chips. Although SHADDR is where the firmware fetches the ending transfer address for a save data pointers request, it is readonly. Setting HADDR has the side effect of also updating SHADDR. Cleanup the output of ahc_dump_card_state() by nulling out the free scb list in the non-paging case. The free list is only used if we must page SCBs. Correct the transmission of cdbs > 12 bytes in length. When swapping HSCBs prior to notifing the sequencer of the new transaction, the bus address pointer for the cdb must also be recalculated to reflect its new location. We now defer the calculation of the cdb address until just before queing it to the card. When pulling transfer negotiation settings out of scratch ram, convert 5MHz/clock doubled settings to 10MHz. Add a new function ahc_qinfifo_requeue_tail() for use by error recovery actions and auto-request sense operations. These operations always occur when the sequencer is paused, so we can avoid the extra expense incurred in the normal SCB queue method. Use the BMOV instruction for all single byte moves on controllers that support it. The bmov instruction is twice as fast as an AND with an immediate of 0xFF as is used on older controllers. Correct a few bugs in ahc_dump_card_state(). If we have hardware assisted queue registers, use them to get the sequencer's idea of the head of the queue. When enumerating the untagged queue, it helps to use the correct index for the queue. aic7xxx.h: Indicate via a feature flag, which controllers can take on both the target and the initiator role at the same time. Add the AHC_SEQUENCER_DEBUG flag. Add the SCB_CDB32_PTR flag used for dealing with cdbs with lengths between 13 and 32 bytes. Add new prototypes. aic7xxx.reg: Allow the SCSIBUSL register to be written to. This is required to fix a selection timeout problem on the 7892/99. Cleanup the sequencer interrupt codes so that all debugging codes are grouped at the end of the list. Correct the definition of the ULTRA_ENB and DISC_DSB locations in scratch ram. This prevented the driver from properly honoring these settings when no serial eeprom was available. Remove an unused sequencer flag. aic7xxx.seq: Just before a potential select-out, clear the SCSIBUSL register. Occasionally, during a selection timeout, the contents of the register may be presented on the bus, causing much confusion. Add sequencer diagnostic code to detect software and or hardware bugs. The code attempts to verify most list operations so any corruption is caught before it occurs. We also track information about why a particular reconnection request was rejected. Don't clobber the digital REQ/ACK filter setting in SXFRCTL0 when clearing the channel. Fix a target mode bug that would cause us to return busy status instead of queue full in respnse to a tagged transaction. Cleanup the overrun case. It turns out that by simply butting the chip in bitbucket mode, it will ack any bytes until the phase changes. This drasticaly simplifies things. Prior to leaving the data phase, make sure that the S/G preload queue is empty. Remove code to place a request sense request on the waiting queue. This is all handled by the kernel now. Change the semantics of "findSCB". In the past, findSCB ensured that a freshly paged in SCB appeared on the disconnected list. The problem with this is that there is no guarantee that the paged in SCB is for a disconnected transation. We now defer any list manipulation to the caller who usually discards the SCB via the free list. Inline some busy target table operations. Add a critical section to protect adding an SCB to the disconnected list. aic7xxx_freebsd.c: Handle changes in the transfer negotiation setting API to filter incoming requests. No filtering is necessary for "goal" requests from the XPT. Set the SCB_CDB32_PTR flag when queing a transaction with a large cdb. In ahc_timeout, only take action if the active SCB is the timedout SCB. This deals with the case of two transactions to the same device with different timeout values. Use ahc_qinfifo_requeu_tail() instead of home grown version. aic7xxx_inline.h: Honor SCB_CDB32_PTR when queuing a new request. aic7xxx_pci.c: Use the maximum data fifo threshold for all chips.
413 lines
12 KiB
C
413 lines
12 KiB
C
/*
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* Inline routines shareable across OS platforms.
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*
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/src/aic7xxx/aic7xxx_inline.h#5 $
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*
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* $FreeBSD$
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*/
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#ifndef _AIC7XXX_INLINE_H_
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#define _AIC7XXX_INLINE_H_
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/************************* Sequencer Execution Control ************************/
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static __inline int sequencer_paused(struct ahc_softc *ahc);
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static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
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static __inline void pause_sequencer(struct ahc_softc *ahc);
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static __inline void unpause_sequencer(struct ahc_softc *ahc);
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/*
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* Work around any chip bugs related to halting sequencer execution.
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* On Ultra2 controllers, we must clear the CIOBUS stretch signal by
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* reading a register that will set this signal and deassert it.
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* Without this workaround, if the chip is paused, by an interrupt or
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* manual pause while accessing scb ram, accesses to certain registers
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* will hang the system (infinite pci retries).
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*/
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static __inline void
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ahc_pause_bug_fix(struct ahc_softc *ahc)
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{
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if ((ahc->features & AHC_ULTRA2) != 0)
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(void)ahc_inb(ahc, CCSCBCTL);
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}
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/*
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* Determine whether the sequencer has halted code execution.
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* Returns non-zero status if the sequencer is stopped.
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*/
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static __inline int
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sequencer_paused(struct ahc_softc *ahc)
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{
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return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
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}
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/*
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* Request that the sequencer stop and wait, indefinitely, for it
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* to stop. The sequencer will only acknowledge that it is paused
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* once it has reached an instruction boundary and PAUSEDIS is
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* cleared in the SEQCTL register. The sequencer may use PAUSEDIS
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* for critical sections.
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*/
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static __inline void
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pause_sequencer(struct ahc_softc *ahc)
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{
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ahc_outb(ahc, HCNTRL, ahc->pause);
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/*
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* Since the sequencer can disable pausing in a critical section, we
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* must loop until it actually stops.
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*/
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while (sequencer_paused(ahc) == 0)
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;
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ahc_pause_bug_fix(ahc);
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}
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/*
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* Allow the sequencer to continue program execution.
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* We check here to ensure that no additional interrupt
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* sources that would cause the sequencer to halt have been
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* asserted. If, for example, a SCSI bus reset is detected
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* while we are fielding a different, pausing, interrupt type,
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* we don't want to release the sequencer before going back
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* into our interrupt handler and dealing with this new
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* condition.
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*/
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static __inline void
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unpause_sequencer(struct ahc_softc *ahc)
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{
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if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
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ahc_outb(ahc, HCNTRL, ahc->unpause);
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}
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/*********************** Untagged Transaction Routines ************************/
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u_int ahc_index_busy_tcl(struct ahc_softc *ahc,
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u_int tcl, int unbusy);
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static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
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static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
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/*
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* Block our completion routine from starting the next untagged
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* transaction for this target or target lun.
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*/
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static __inline void
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ahc_freeze_untagged_queues(struct ahc_softc *ahc)
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{
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if ((ahc->features & AHC_SCB_BTT) == 0)
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ahc->untagged_queue_lock++;
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}
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/*
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* Allow the next untagged transaction for this target or target lun
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* to be executed. We use a counting semaphore to allow the lock
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* to be acquired recursively. Once the count drops to zero, the
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* transaction queues will be run.
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*/
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static __inline void
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ahc_release_untagged_queues(struct ahc_softc *ahc)
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{
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if ((ahc->features & AHC_SCB_BTT) == 0) {
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ahc->untagged_queue_lock--;
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if (ahc->untagged_queue_lock == 0)
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ahc_run_untagged_queues(ahc);
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}
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}
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/************************** Memory mapping routines ***************************/
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static __inline struct ahc_dma_seg *
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ahc_sg_bus_to_virt(struct scb *scb,
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uint32_t sg_busaddr);
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static __inline uint32_t
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ahc_sg_virt_to_bus(struct scb *scb,
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struct ahc_dma_seg *sg);
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static __inline uint32_t
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ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
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static __inline struct ahc_dma_seg *
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ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
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{
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int sg_index;
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sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
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/* sg_list_phys points to entry 1, not 0 */
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sg_index++;
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return (&scb->sg_list[sg_index]);
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}
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static __inline uint32_t
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ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
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{
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int sg_index;
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/* sg_list_phys points to entry 1, not 0 */
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sg_index = sg - &scb->sg_list[1];
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return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
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}
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static __inline uint32_t
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ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
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{
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return (ahc->scb_data->hscb_busaddr
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+ (sizeof(struct hardware_scb) * index));
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}
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/******************************** Debugging ***********************************/
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static __inline char *ahc_name(struct ahc_softc *ahc);
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static __inline char *
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ahc_name(struct ahc_softc *ahc)
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{
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return (ahc->name);
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}
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/*********************** Miscelaneous Support Functions ***********************/
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static __inline int ahc_check_residual(struct scb *scb);
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static __inline struct ahc_initiator_tinfo *
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ahc_fetch_transinfo(struct ahc_softc *ahc,
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char channel, u_int our_id,
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u_int remote_id,
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struct tmode_tstate **tstate);
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static __inline struct scb*
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ahc_get_scb(struct ahc_softc *ahc);
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static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
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static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
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/*
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* Determine whether the sequencer reported a residual
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* for this SCB/transaction.
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*/
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static __inline int
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ahc_check_residual(struct scb *scb)
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{
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struct status_pkt *sp;
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sp = &scb->hscb->shared_data.status;
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if ((scb->hscb->sgptr & SG_RESID_VALID) != 0)
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return (1);
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return (0);
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}
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/*
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* Return pointers to the transfer negotiation information
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* for the specified our_id/remote_id pair.
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*/
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static __inline struct ahc_initiator_tinfo *
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ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
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u_int remote_id, struct tmode_tstate **tstate)
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{
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/*
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* Transfer data structures are stored from the perspective
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* of the target role. Since the parameters for a connection
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* in the initiator role to a given target are the same as
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* when the roles are reversed, we pretend we are the target.
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*/
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if (channel == 'B')
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our_id += 8;
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*tstate = ahc->enabled_targets[our_id];
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return (&(*tstate)->transinfo[remote_id]);
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}
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/*
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* Get a free scb. If there are none, see if we can allocate a new SCB.
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*/
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static __inline struct scb *
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ahc_get_scb(struct ahc_softc *ahc)
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{
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struct scb *scb;
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if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
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ahc_alloc_scbs(ahc);
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scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
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if (scb == NULL)
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return (NULL);
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}
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SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
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return (scb);
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}
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/*
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* Return an SCB resource to the free list.
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*/
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static __inline void
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ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
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{
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struct hardware_scb *hscb;
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hscb = scb->hscb;
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/* Clean up for the next user */
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ahc->scb_data->scbindex[hscb->tag] = NULL;
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scb->flags = SCB_FREE;
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hscb->control = 0;
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SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
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/* Notify the OSM that a resource is now available. */
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ahc_platform_scb_free(ahc, scb);
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}
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static __inline struct scb *
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ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
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{
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return (ahc->scb_data->scbindex[tag]);
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}
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/*
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* Tell the sequencer about a new transaction to execute.
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*/
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static __inline void
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ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
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{
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struct hardware_scb *q_hscb;
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u_int saved_tag;
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/*
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* Our queuing method is a bit tricky. The card
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* knows in advance which HSCB to download, and we
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* can't disappoint it. To achieve this, the next
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* SCB to download is saved off in ahc->next_queued_scb.
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* When we are called to queue "an arbitrary scb",
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* we copy the contents of the incoming HSCB to the one
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* the sequencer knows about, swap HSCB pointers and
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* finally assigne the SCB to the tag indexed location
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* in the scb_array. This makes sure that we can still
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* locate the correct SCB by SCB_TAG.
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*
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* Start by copying the payload without perterbing
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* the tag number. Also set the hscb id for the next
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* SCB to download.
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*/
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q_hscb = ahc->next_queued_scb->hscb;
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saved_tag = q_hscb->tag;
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memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
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if ((scb->flags & SCB_CDB32_PTR) != 0) {
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q_hscb->shared_data.cdb_ptr =
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ahc_hscb_busaddr(ahc, q_hscb->tag)
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+ offsetof(struct hardware_scb, cdb32);
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}
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q_hscb->tag = saved_tag;
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q_hscb->next = scb->hscb->tag;
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/* Now swap HSCB pointers. */
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ahc->next_queued_scb->hscb = scb->hscb;
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scb->hscb = q_hscb;
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/* Now define the mapping from tag to SCB in the scbindex */
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ahc->scb_data->scbindex[scb->hscb->tag] = scb;
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if (scb->hscb->tag == SCB_LIST_NULL
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|| scb->hscb->next == SCB_LIST_NULL)
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panic("Attempt to queue invalid SCB tag %x:%x\n",
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scb->hscb->tag, scb->hscb->next);
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/*
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* Keep a history of SCBs we've downloaded in the qinfifo.
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*/
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ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
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if ((ahc->features & AHC_QUEUE_REGS) != 0) {
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ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
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} else {
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if ((ahc->features & AHC_AUTOPAUSE) == 0)
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pause_sequencer(ahc);
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ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
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if ((ahc->features & AHC_AUTOPAUSE) == 0)
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unpause_sequencer(ahc);
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}
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}
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/************************** Interrupt Processing ******************************/
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static __inline void ahc_intr(struct ahc_softc *ahc);
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/*
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* Catch an interrupt from the adapter
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*/
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static __inline void
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ahc_intr(struct ahc_softc *ahc)
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{
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u_int intstat;
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intstat = ahc_inb(ahc, INTSTAT);
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/*
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* Any interrupts to process?
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*/
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#if AHC_PCI_CONFIG > 0
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if ((intstat & INT_PEND) == 0) {
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if ((ahc->chip & AHC_PCI) != 0
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&& (ahc->unsolicited_ints > 500)) {
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if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
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ahc_pci_intr(ahc);
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ahc->unsolicited_ints = 0;
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} else {
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ahc->unsolicited_ints++;
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}
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return;
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} else {
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ahc->unsolicited_ints = 0;
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}
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#else
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if ((intstat & INT_PEND) == 0)
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return;
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#endif
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if (intstat & CMDCMPLT) {
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ahc_outb(ahc, CLRINT, CLRCMDINT);
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/*
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* Ensure that the chip sees that we've cleared
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* this interrupt before we walk the output fifo.
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* Otherwise, we may, due to posted bus writes,
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* clear the interrupt after we finish the scan,
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* and after the sequencer has added new entries
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* and asserted the interrupt again.
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*/
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ahc_flush_device_writes(ahc);
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ahc_run_qoutfifo(ahc);
|
|
#ifdef AHC_TARGET_MODE
|
|
if ((ahc->flags & AHC_TARGETROLE) != 0)
|
|
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
|
|
#endif
|
|
}
|
|
if (intstat & BRKADRINT)
|
|
ahc_handle_brkadrint(ahc);
|
|
|
|
if ((intstat & (SEQINT|SCSIINT)) != 0)
|
|
ahc_pause_bug_fix(ahc);
|
|
|
|
if ((intstat & SEQINT) != 0)
|
|
ahc_handle_seqint(ahc, intstat);
|
|
|
|
if ((intstat & SCSIINT) != 0)
|
|
ahc_handle_scsiint(ahc, intstat);
|
|
}
|
|
|
|
#endif /* _AIC7XXX_INLINE_H_ */
|