212 lines
6.9 KiB
C
212 lines
6.9 KiB
C
/*
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* Interface to the generic driver for the aic7xxx based adaptec
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* SCSI controllers. This is used to implement product specific
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* probe and attach routines.
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*
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* Copyright (c) 1994, 1995 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Justin T. Gibbs.
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* 4. Modifications may be freely made to this file if the above conditions
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* are met.
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*
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* $Id: aic7xxx.h,v 1.18 1996/01/07 19:24:33 gibbs Exp $
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*/
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#ifndef _AIC7XXX_H_
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#define _AIC7XXX_H_
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#include "ahc.h" /* for NAHC from config */
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#define AHC_NSEG 256 /* number of dma segments supported */
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#define AHC_SCB_MAX 255 /*
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* Up to 255 SCBs on some types of aic7xxx
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* based boards. The aic7870 have 16 internal
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* SCBs, but external SRAM bumps this to 255.
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* The aic7770 family have only 4, and the
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* aic7850 has only 3.
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*/
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/* #define AHCDEBUG */
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extern int bootverbose;
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typedef unsigned long int physaddr;
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extern u_long ahc_unit;
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struct ahc_dma_seg {
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physaddr addr;
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long len;
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};
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typedef enum {
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AHC_NONE = 0x000,
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AHC_ULTRA = 0x001, /* Supports 20MHz Transfers */
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AHC_WIDE = 0x002, /* Wide Channel */
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AHC_TWIN = 0x008, /* Twin Channel */
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AHC_AIC7770 = 0x010,
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AHC_AIC7850 = 0x020,
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AHC_AIC7870 = 0x040,
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AHC_AIC7880 = 0x041,
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AHC_AIC78X0 = 0x060, /* PCI Based Controller */
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AHC_274 = 0x110, /* EISA Based Controller */
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AHC_284 = 0x210, /* VL/ISA Based Controller */
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AHC_294 = 0x440, /* PCI Based Controller */
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AHC_294U = 0x441, /* ULTRA PCI Based Controller */
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AHC_394 = 0x840, /* Twin Channel PCI Controller */
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AHC_394U = 0x841, /* Twin, ULTRA Channel PCI Controller */
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}ahc_type;
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typedef enum {
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AHC_FNONE = 0x00,
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AHC_INIT = 0x01,
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AHC_RUNNING = 0x02,
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AHC_USEDEFAULTS = 0x04, /*
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* For cards without an seeprom
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* or a BIOS to initialize the chip's
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* SRAM, we use the default chip and
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* target settings.
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*/
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AHC_EXTSCB = 0x10, /* External SCBs present */
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AHC_CHNLB = 0x20, /*
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* Second controller on 3940
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* Also encodes the offset in the
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* SEEPROM for CHNLB info (32)
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*/
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}ahc_flag;
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/*
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* The driver keeps up to MAX_SCB scb structures per card in memory. Only the
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* first 26 bytes of the structure need to be transfered to the card during
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* normal operation. The remaining fields (next_waiting and host_scb) are
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* initialized the first time an SCB is allocated in get_scb(). The fields
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* starting at byte 32 are used for kernel level bookeeping.
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*/
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struct scb {
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/* ------------ Begin hardware supported fields ---------------- */
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/*0*/ u_char control;
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/*1*/ u_char target_channel_lun; /* 4/1/3 bits */
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/*2*/ u_char target_status;
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/*3*/ u_char SG_segment_count;
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/*4*/ physaddr SG_list_pointer;
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/*8*/ u_char residual_SG_segment_count;
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/*9*/ u_char residual_data_count[3];
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/*12*/ physaddr data;
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/*16*/ u_long datalen; /* Really only three bits, but its
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* faster to treat it as a long on
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* a quad boundary.
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*/
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/*20*/ physaddr cmdpointer;
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/*24*/ u_char cmdlen;
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/*25*/ u_char RESERVED[2]; /* must be zero */
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#define SCB_PIO_TRANSFER_SIZE 26 /*
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* amount we need to upload/download
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* via rep in/outsb to perform
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* a request sense. The second
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* RESERVED byte is initialized to
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* 0 in get_scb().
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*/
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/*27*/ u_char next_waiting; /* Used to thread SCBs awaiting
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* selection
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*/
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/*28*/ physaddr host_scb;
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#define SCB_HARDWARE_SIZE 32
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/*-----------------end of hardware supported fields----------------*/
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struct scb *next; /* in free list */
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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int flags;
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#define SCB_FREE 0x00
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#define SCB_ACTIVE 0x01
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#define SCB_ABORTED 0x02
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#define SCB_DEVICE_RESET 0x04
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#define SCB_IMMED 0x08
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#define SCB_SENSE 0x10
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int position; /* Position in scbarray */
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struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed));
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struct scsi_sense sense_cmd; /* SCSI command block */
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};
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struct ahc_data {
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int unit;
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ahc_type type;
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ahc_flag flags;
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u_long baseport;
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struct scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */
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struct scb *free_scb;
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int our_id; /* our scsi id */
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int our_id_b; /* B channel scsi id */
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int vect;
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struct scb *immed_ecb; /* an outstanding immediete command */
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struct scsi_link sc_link;
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struct scsi_link sc_link_b; /* Second bus for Twin channel cards */
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u_short needsdtr_orig; /* Targets we initiate sync neg with */
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u_short needwdtr_orig; /* Targets we initiate wide neg with */
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u_short needsdtr; /* Current list of negotiated targets */
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u_short needwdtr; /* Current list of negotiated targets */
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u_short sdtrpending; /* Pending SDTR to these targets */
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u_short wdtrpending; /* Pending WDTR to these targets */
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u_short tagenable; /* Targets that can handle tagqueing */
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u_short discenable; /* Targets allowed to disconnect */
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int numscbs;
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int activescbs;
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u_char maxscbs;
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u_char unpause;
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u_char pause;
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};
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/* Different debugging levels used when AHC_DEBUG is defined */
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#define AHC_SHOWMISC 0x0001
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#define AHC_SHOWCMDS 0x0002
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#define AHC_SHOWSCBS 0x0004
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#define AHC_SHOWABORTS 0x0008
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#define AHC_SHOWSENSE 0x0010
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#define AHC_SHOWSCBCNT 0x0020
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/* #define AHC_DEBUG */
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extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */
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/*
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* Since the sequencer can disable pausing in a critical section, we
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* must loop until it actually stops.
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* XXX Should add a timeout in here??
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*/
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#define PAUSE_SEQUENCER(ahc) \
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outb(HCNTRL + ahc->baseport, ahc->pause); \
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\
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while ((inb(HCNTRL + ahc->baseport) & PAUSE) == 0) \
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;
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#define UNPAUSE_SEQUENCER(ahc) \
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outb( HCNTRL + ahc->baseport, ahc->unpause )
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/*
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* Restart the sequencer program from address zero
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*/
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#define RESTART_SEQUENCER(ahc) \
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do { \
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outb( SEQCTL + ahc->baseport, SEQRESET|FASTMODE ); \
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} while (inb(SEQADDR0 + ahc->baseport) != 0 && \
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inb(SEQADDR1 + ahc->baseport != 0)); \
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\
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UNPAUSE_SEQUENCER(ahc);
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void ahc_reset __P((u_long iobase));
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struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_flag flags));
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void ahc_free __P((struct ahc_data *));
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int ahc_init __P((struct ahc_data *));
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int ahc_attach __P((struct ahc_data *));
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void ahc_intr __P((void *arg));
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#endif /* _AIC7XXX_H_ */
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