566 lines
14 KiB
C
566 lines
14 KiB
C
/*
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* Product specific probe and attach routines for:
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* 3940, 2940, aic7870, and aic7850 SCSI controllers
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*
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* Copyright (c) 1995 Justin T. Gibbs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Justin T. Gibbs.
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* 4. Modifications may be freely made to this file if the above conditions
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* are met.
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*
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* $Id: aic7870.c,v 1.23 1996/01/09 16:14:53 gibbs Exp $
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*/
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#include <pci.h>
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#if NPCI > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <machine/clock.h>
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#include <i386/scsi/aic7xxx.h>
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#include <i386/scsi/93cx6.h>
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#include <dev/aic7xxx/aic7xxx_reg.h>
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#define PCI_BASEADR0 PCI_MAP_REG_START
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#define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul
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#define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul
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#define DEVCONFIG 0x40
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#define MPORTMODE 0x00000400ul /* aic7870 only */
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#define RAMPSM 0x00000200ul /* aic7870 only */
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#define VOLSENSE 0x00000100ul
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#define SCBRAMSEL 0x00000080ul
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#define MRDCEN 0x00000040ul
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#define EXTSCBTIME 0x00000020ul /* aic7870 only */
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#define EXTSCBPEN 0x00000010ul /* aic7870 only */
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#define BERREN 0x00000008ul
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#define DACEN 0x00000004ul
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#define STPWLEVEL 0x00000002ul
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#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
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#define CSIZE_LATTIME 0x0c
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#define CACHESIZE 0x0000003ful /* only 5 bits */
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#define LATTIME 0x0000ff00ul
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/*
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* Define the format of the aic78X0 SEEPROM registers (16 bits).
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*
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*/
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struct seeprom_config {
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/*
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* SCSI ID Configuration Flags
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*/
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#define CFXFER 0x0007 /* synchronous transfer rate */
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#define CFSYNCH 0x0008 /* enable synchronous transfer */
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#define CFDISC 0x0010 /* enable disconnection */
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#define CFWIDEB 0x0020 /* wide bus device */
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/* UNUSED 0x00C0 */
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#define CFSTART 0x0100 /* send start unit SCSI command */
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#define CFINCBIOS 0x0200 /* include in BIOS scan */
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#define CFRNFOUND 0x0400 /* report even if not found */
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/* UNUSED 0xf800 */
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unsigned short device_flags[16]; /* words 0-15 */
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/*
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* BIOS Control Bits
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*/
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#define CFSUPREM 0x0001 /* support all removeable drives */
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#define CFSUPREMB 0x0002 /* support removeable drives for boot only */
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#define CFBIOSEN 0x0004 /* BIOS enabled */
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/* UNUSED 0x0008 */
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#define CFSM2DRV 0x0010 /* support more than two drives */
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/* UNUSED 0x0060 */
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#define CFEXTEND 0x0080 /* extended translation enabled */
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/* UNUSED 0xff00 */
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unsigned short bios_control; /* word 16 */
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/*
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* Host Adapter Control Bits
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*/
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/* UNUSED 0x0001 */
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#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */
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#define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */
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#define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */
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#define CFSPARITY 0x0010 /* SCSI parity */
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/* UNUSED 0x0020 */
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#define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */
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/* UNUSED 0xff80 */
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unsigned short adapter_control; /* word 17 */
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/*
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* Bus Release, Host Adapter ID
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*/
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#define CFSCSIID 0x000f /* host adapter SCSI ID */
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/* UNUSED 0x00f0 */
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#define CFBRTIME 0xff00 /* bus release time */
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unsigned short brtime_id; /* word 18 */
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/*
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* Maximum targets
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*/
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#define CFMAXTARG 0x00ff /* maximum targets */
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/* UNUSED 0xff00 */
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unsigned short max_targets; /* word 19 */
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unsigned short res_1[11]; /* words 20-30 */
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unsigned short checksum; /* word 31 */
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};
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static char* aic7870_probe __P((pcici_t tag, pcidi_t type));
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static void aic7870_attach __P((pcici_t config_id, int unit));
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static int load_seeprom __P((struct ahc_data *ahc));
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static int acquire_seeprom __P((u_long offset, u_short CS, u_short CK,
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u_short DO, u_short DI, u_short RDY,
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u_short MS));
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static void release_seeprom __P((u_long offset, u_short CS, u_short CK,
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u_short DO, u_short DI, u_short RDY,
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u_short MS));
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static u_char aic3940_count;
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static struct pci_device ahc_pci_driver = {
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"ahc",
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aic7870_probe,
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aic7870_attach,
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&ahc_unit,
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NULL
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};
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DATA_SET (pcidevice_set, ahc_pci_driver);
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static char*
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aic7870_probe (pcici_t tag, pcidi_t type)
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{
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switch(type) {
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case PCI_DEVICE_ID_ADAPTEC_3940U:
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return ("Adaptec 3940 Ultra SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_3940:
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return ("Adaptec 3940 SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944U:
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return ("Adaptec 2944 Ultra SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940U:
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return ("Adaptec 2940 Ultra SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944:
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return ("Adaptec 2944 SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940:
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return ("Adaptec 2940 SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7880:
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return ("Adaptec aic7880 Ultra SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7870:
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return ("Adaptec aic7870 SCSI host adapter");
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7850:
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return ("Adaptec aic7850 SCSI host adapter");
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break;
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default:
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break;
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}
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return (0);
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}
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static void
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aic7870_attach(config_id, unit)
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pcici_t config_id;
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int unit;
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{
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u_long io_port;
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u_long id;
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unsigned opri = 0;
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ahc_type ahc_t = AHC_NONE;
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ahc_flag ahc_f = AHC_FNONE;
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struct ahc_data *ahc;
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if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0)))
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return;
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/*
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* The first bit of PCI_BASEADR0 is always
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* set hence we mask it off.
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*/
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io_port &= 0xfffffffe;
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switch ((id = pci_conf_read(config_id, PCI_ID_REG))) {
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case PCI_DEVICE_ID_ADAPTEC_3940U:
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case PCI_DEVICE_ID_ADAPTEC_3940:
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if (id == PCI_DEVICE_ID_ADAPTEC_3940U)
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ahc_t = AHC_394U;
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else
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ahc_t = AHC_394;
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aic3940_count++;
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if(!(aic3940_count & 0x01))
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/* Even count implies second channel */
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ahc_f |= AHC_CHNLB;
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/* Even though it doesn't turn on RAMPS, it has them */
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ahc_f |= AHC_EXTSCB;
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944U:
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case PCI_DEVICE_ID_ADAPTEC_2940U:
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ahc_t = AHC_294U;
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944:
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case PCI_DEVICE_ID_ADAPTEC_2940:
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ahc_t = AHC_294;
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7880:
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ahc_t = AHC_AIC7880;
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7870:
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ahc_t = AHC_AIC7870;
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7850:
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ahc_t = AHC_AIC7850;
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break;
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default:
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break;
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}
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ahc_reset(io_port);
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if(ahc_t & AHC_AIC7870){
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u_long devconfig = pci_conf_read(config_id, DEVCONFIG);
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if(devconfig & (RAMPSM)) {
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/*
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* External SRAM present. Have the probe walk
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* the SCBs to see how much SRAM we have and set
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* the number of SCBs accordingly. We have to
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* turn off SCBRAMSEL to access the external
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* SCB SRAM.
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*
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* It seems that early versions of the aic7870
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* didn't use these bits, hence the hack for the
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* 3940 above. I would guess that recent 3940s
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* using later aic7870 or aic7880 chips do
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* actually set RAMPSM.
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*
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* The documentation isn't clear, but it sounds
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* like the value written to devconfig must not
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* have RAMPSM set. The second sixteen bits of
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* the register are R/O anyway, so it shouldn't
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* affect RAMPSM either way.
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*/
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devconfig &= ~(RAMPSM|SCBRAMSEL);
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pci_conf_write(config_id, DEVCONFIG, devconfig);
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ahc_f |= AHC_EXTSCB;
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}
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}
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/*
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* Ensure that we are using good values for the PCI burst size
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* and latency timer.
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*/
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{
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u_long csize_lattime = pci_conf_read(config_id, CSIZE_LATTIME);
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if((csize_lattime & CACHESIZE) == 0) {
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/* default to 8DWDs. What's the PCI define for this? */
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csize_lattime |= 8;
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}
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if((csize_lattime & LATTIME) == 0) {
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/* Default to 64 PCLKS (is this a good value?) */
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/* This may also be availble in the SEEPROM?? */
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csize_lattime |= (64 << 8);
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}
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if(bootverbose)
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printf("ahc%d: BurstLen = %dDWDs, "
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"Latency Timer = %dPCLKS\n",
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unit,
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csize_lattime & CACHESIZE,
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(csize_lattime >> 8) & 0xff);
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pci_conf_write(config_id, CSIZE_LATTIME, csize_lattime);
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}
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if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f)))
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return; /* XXX PCI code should take return status */
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if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) {
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ahc_free(ahc);
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return;
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}
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/*
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* Protect ourself from spurrious interrupts during
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* intialization.
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*/
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opri = splbio();
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/*
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* Do aic7870/aic7880/aic7850 specific initialization
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*/
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{
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u_char sblkctl;
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char *id_string;
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u_long iobase = ahc->baseport;
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switch(ahc->type) {
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case AHC_394U:
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case AHC_294U:
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case AHC_AIC7880:
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{
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id_string = "aic7880 ";
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load_seeprom(ahc);
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ahc->maxscbs = 16;
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break;
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}
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case AHC_394:
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case AHC_294:
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case AHC_AIC7870:
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{
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id_string = "aic7870 ";
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load_seeprom(ahc);
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ahc->maxscbs = 16;
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break;
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}
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case AHC_AIC7850:
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{
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id_string = "aic7850 ";
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ahc->maxscbs = 3;
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/* Assume there is no BIOS for these cards? */
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ahc->flags |= AHC_USEDEFAULTS;
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break;
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}
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default:
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{
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printf("ahc: Unknown controller type. Ignoring.\n");
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return;
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break;
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}
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}
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printf("ahc%d: %s", unit, id_string);
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/*
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* Take the LED out of diagnostic mode
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*/
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sblkctl = inb(SBLKCTL + iobase);
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outb(SBLKCTL + iobase, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
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/*
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* I don't know where this is set in the SEEPROM or by the
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* BIOS, so we default to 100%.
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*/
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outb(DSPCISTATUS + iobase, DFTHRSH_100);
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if(ahc->flags & AHC_USEDEFAULTS) {
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/*
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* PCI Adapter default setup
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* Should only be used if the adapter does not have
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* an SEEPROM and we don't think a BIOS was installed.
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*/
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/* Set the host ID */
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outb(SCSICONF + iobase, 7);
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/* In case we are a wide card */
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outb(SCSICONF + 1 + iobase, 7);
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}
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if(ahc->flags & AHC_EXTSCB) {
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/*
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* This adapter has external SCB memory.
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* Walk the SCBs to determine how many there are.
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*/
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int i;
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for(i = 0; i < AHC_SCB_MAX; i++) {
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outb(SCBPTR + iobase, i);
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outb(SCBARRAY + iobase, 0xaa);
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if(inb(SCBARRAY + iobase) == 0xaa){
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outb(SCBARRAY + iobase, 0x55);
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if(inb(SCBARRAY + iobase) == 0x55) {
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continue;
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}
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}
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break;
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}
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ahc->maxscbs = i;
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}
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}
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if(ahc_init(ahc)){
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ahc_free(ahc);
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splx(opri);
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return; /* XXX PCI code should take return status */
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}
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splx(opri);
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ahc_attach(ahc);
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return;
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}
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/*
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* Read the SEEPROM. Return 0 on failure
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*/
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int
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load_seeprom(ahc)
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struct ahc_data *ahc;
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{
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struct seeprom_config sc;
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u_short *scarray = (u_short *)≻
|
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u_short checksum = 0;
|
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u_long iobase = ahc->baseport;
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u_char host_id;
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int have_seeprom, retval;
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if(bootverbose)
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printf("ahc%d: Reading SEEPROM...", ahc->unit);
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have_seeprom = acquire_seeprom(iobase + SEECTL, SEECS,
|
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SEECK, SEEDO, SEEDI, SEERDY, SEEMS);
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if (have_seeprom) {
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have_seeprom = read_seeprom(iobase + SEECTL,
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(u_short *)&sc,
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ahc->flags & AHC_CHNLB,
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sizeof(sc)/2, SEECS, SEECK, SEEDO,
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SEEDI, SEERDY, SEEMS);
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release_seeprom(iobase + SEECTL, SEECS, SEECK, SEEDO,
|
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SEEDI, SEERDY, SEEMS);
|
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if (have_seeprom) {
|
|
/* Check checksum */
|
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int i;
|
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|
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for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1)
|
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checksum = checksum + scarray[i];
|
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if (checksum != sc.checksum) {
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printf ("checksum error");
|
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have_seeprom = 0;
|
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}
|
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else {
|
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if(bootverbose)
|
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printf("done.\n");
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host_id = (sc.brtime_id & CFSCSIID);
|
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}
|
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}
|
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}
|
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if (!have_seeprom) {
|
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printf("\nahc%d: SEEPROM read failed, "
|
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"using leftover BIOS values\n", ahc->unit);
|
|
retval = 0;
|
|
|
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host_id = 0x7; /* Assume a default */
|
|
/*
|
|
* If we happen to be an ULTRA card,
|
|
* default to non-ultra mode.
|
|
*/
|
|
ahc->type &= ~AHC_ULTRA;
|
|
}
|
|
else {
|
|
/*
|
|
* Put the data we've collected down into SRAM
|
|
* where ahc_init will find it.
|
|
*/
|
|
int i;
|
|
int max_targ = sc.max_targets & CFMAXTARG;
|
|
|
|
for(i = 0; i <= max_targ; i++){
|
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u_char target_settings;
|
|
target_settings = (sc.device_flags[i] & CFXFER) << 4;
|
|
if (sc.device_flags[i] & CFSYNCH)
|
|
target_settings |= SOFS;
|
|
if (sc.device_flags[i] & CFWIDEB)
|
|
target_settings |= WIDEXFER;
|
|
if (sc.device_flags[i] & CFDISC)
|
|
ahc->discenable |= (0x01 << i);
|
|
outb(TARG_SCRATCH+i+iobase, target_settings);
|
|
}
|
|
outb(DISC_DSB + iobase, ~(ahc->discenable & 0xff));
|
|
outb(DISC_DSB + iobase + 1, ~((ahc->discenable >> 8) & 0xff));
|
|
|
|
host_id = sc.brtime_id & CFSCSIID;
|
|
|
|
if(ahc->type & AHC_ULTRA) {
|
|
/* Should we enable Ultra mode? */
|
|
if(!(sc.adapter_control & CFULTRAEN))
|
|
/* Treat us as a non-ultra card */
|
|
ahc->type &= ~AHC_ULTRA;
|
|
}
|
|
retval = 1;
|
|
}
|
|
/* Set the host ID */
|
|
outb(SCSICONF + iobase, host_id);
|
|
/* In case we are a wide card */
|
|
outb(SCSICONF + 1 + iobase, host_id);
|
|
|
|
return(retval);
|
|
}
|
|
|
|
static int
|
|
acquire_seeprom(offset, CS, CK, DO, DI, RDY, MS)
|
|
u_long offset;
|
|
u_short CS; /* chip select */
|
|
u_short CK; /* clock */
|
|
u_short DO; /* data out */
|
|
u_short DI; /* data in */
|
|
u_short RDY; /* ready */
|
|
u_short MS; /* mode select */
|
|
{
|
|
int wait;
|
|
/*
|
|
* Request access of the memory port. When access is
|
|
* granted, SEERDY will go high. We use a 1 second
|
|
* timeout which should be near 1 second more than
|
|
* is needed. Reason: after the chip reset, there
|
|
* should be no contention.
|
|
*/
|
|
outb(offset, MS);
|
|
wait = 1000; /* 1 second timeout in msec */
|
|
while (--wait && ((inb(offset) & RDY) == 0)) {
|
|
DELAY (1000); /* delay 1 msec */
|
|
}
|
|
if ((inb(offset) & RDY) == 0) {
|
|
outb (offset, 0);
|
|
return (0);
|
|
}
|
|
return(1);
|
|
}
|
|
|
|
static void
|
|
release_seeprom(offset, CS, CK, DO, DI, RDY, MS)
|
|
u_long offset;
|
|
u_short CS; /* chip select */
|
|
u_short CK; /* clock */
|
|
u_short DO; /* data out */
|
|
u_short DI; /* data in */
|
|
u_short RDY; /* ready */
|
|
u_short MS; /* mode select */
|
|
{
|
|
/* Release access to the memory port and the serial EEPROM. */
|
|
outb(offset, 0);
|
|
}
|
|
|
|
#endif /* NPCI > 0 */
|