219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* PCI / PCIe packet engine related structures.
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*
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* <hr>$Revision: 41586 $<hr>
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*/
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#ifndef __CVMX_NPI_H__
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#define __CVMX_NPI_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* PCI / PCIe packet instruction header format
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*/
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typedef union
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{
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uint64_t u64;
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struct
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t r : 1; /**< Packet is RAW */
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uint64_t g : 1; /**< Gather list is used */
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uint64_t dlengsz : 14; /**< Data length / Gather list size */
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uint64_t fsz : 6; /**< Front data size */
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uint64_t qos : 3; /**< POW QoS queue */
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uint64_t grp : 4; /**< POW Group */
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uint64_t rs : 1; /**< Real short */
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cvmx_pow_tag_type_t tt : 2; /**< POW Tag type */
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uint64_t tag : 32; /**< POW 32 bit tag */
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#else
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uint64_t tag : 32;
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cvmx_pow_tag_type_t tt : 2;
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uint64_t rs : 1;
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uint64_t grp : 4;
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uint64_t qos : 3;
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uint64_t fsz : 6;
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uint64_t dlengsz : 14;
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uint64_t g : 1;
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uint64_t r : 1;
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#endif
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} s;
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} cvmx_npi_inst_hdr_t;
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/**
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* PCI / PCIe packet data pointer formats 0-3
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*/
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typedef union
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{
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uint64_t dptr0;
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struct
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t es : 2; /**< Endian swap mode */
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uint64_t ns : 1; /**< No snoop */
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uint64_t ro : 1; /**< Relaxed ordering */
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uint64_t addr : 60; /**< PCI/PCIe address */
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#else
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uint64_t addr : 60;
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uint64_t ro : 1;
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uint64_t ns : 1;
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uint64_t es : 2;
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#endif
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} dptr1;
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struct
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t pm : 2; /**< Parse mode */
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uint64_t sl : 7; /**< Skip length */
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uint64_t addr : 55; /**< PCI/PCIe address */
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#else
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uint64_t addr : 55;
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uint64_t sl : 7;
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uint64_t pm : 2;
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#endif
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} dptr2;
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struct
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t es : 2; /**< Endian swap mode */
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uint64_t ns : 1; /**< No snoop */
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uint64_t ro : 1; /**< Relaxed ordering */
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uint64_t pm : 2; /**< Parse mode */
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uint64_t sl : 7; /**< Skip length */
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uint64_t addr : 51; /**< PCI/PCIe address */
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#else
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uint64_t addr : 51;
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uint64_t sl : 7;
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uint64_t pm : 2;
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uint64_t ro : 1;
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uint64_t ns : 1;
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uint64_t es : 2;
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#endif
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} dptr3;
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} cvmx_npi_dptr_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_NPI_H__ */
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