add35ed5b8
to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
402 lines
10 KiB
C
402 lines
10 KiB
C
/*-
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* Copyright (c) 2011 The FreeBSD Foundation
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* All rights reserved.
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*
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* Developed by Damjan Marion <damjan.marion@gmail.com>
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*
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* Based on OMAP4 GIC code by Ben Gray
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/smp.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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/* We are using GICv2 register naming */
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/* Distributor Registers */
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#define GICD_CTLR 0x000 /* v1 ICDDCR */
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#define GICD_TYPER 0x004 /* v1 ICDICTR */
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#define GICD_IIDR 0x008 /* v1 ICDIIDR */
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#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
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#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
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#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
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#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
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#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
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#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
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#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
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#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
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#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
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#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
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/* CPU Registers */
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#define GICC_CTLR 0x0000 /* v1 ICCICR */
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#define GICC_PMR 0x0004 /* v1 ICCPMR */
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#define GICC_BPR 0x0008 /* v1 ICCBPR */
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#define GICC_IAR 0x000C /* v1 ICCIAR */
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#define GICC_EOIR 0x0010 /* v1 ICCEOIR */
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#define GICC_RPR 0x0014 /* v1 ICCRPR */
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#define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
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#define GICC_ABPR 0x001C /* v1 ICCABPR */
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#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
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/* First bit is a polarity bit (0 - low, 1 - high) */
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#define GICD_ICFGR_POL_LOW (0 << 0)
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#define GICD_ICFGR_POL_HIGH (1 << 0)
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#define GICD_ICFGR_POL_MASK 0x1
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/* Second bit is a trigger bit (0 - level, 1 - edge) */
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#define GICD_ICFGR_TRIG_LVL (0 << 1)
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#define GICD_ICFGR_TRIG_EDGE (1 << 1)
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#define GICD_ICFGR_TRIG_MASK 0x2
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struct arm_gic_softc {
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struct resource * gic_res[3];
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bus_space_tag_t gic_c_bst;
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bus_space_tag_t gic_d_bst;
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bus_space_handle_t gic_c_bsh;
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bus_space_handle_t gic_d_bsh;
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uint8_t ver;
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device_t dev;
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struct mtx mutex;
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uint32_t nirqs;
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};
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static struct resource_spec arm_gic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
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{ -1, 0 }
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};
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static struct arm_gic_softc *arm_gic_sc = NULL;
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#define gic_c_read_4(reg) \
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bus_space_read_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg)
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#define gic_c_write_4(reg, val) \
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bus_space_write_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg, val)
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#define gic_d_read_4(reg) \
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bus_space_read_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg)
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#define gic_d_write_4(reg, val) \
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bus_space_write_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg, val)
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static int gic_config_irq(int irq, enum intr_trigger trig,
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enum intr_polarity pol);
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static void gic_post_filter(void *);
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static int
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arm_gic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "arm,gic"))
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return (ENXIO);
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device_set_desc(dev, "ARM Generic Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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void
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gic_init_secondary(void)
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{
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int i, nirqs;
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/* Get the number of interrupts */
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nirqs = gic_d_read_4(GICD_TYPER);
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nirqs = 32 * ((nirqs & 0x1f) + 1);
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for (i = 0; i < nirqs; i += 4)
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gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
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/* Set all the interrupts to be in Group 0 (secure) */
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for (i = 0; i < nirqs; i += 32) {
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gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
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}
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/* Enable CPU interface */
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gic_c_write_4(GICC_CTLR, 1);
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/* Set priority mask register. */
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gic_c_write_4(GICC_PMR, 0xff);
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/* Enable interrupt distribution */
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gic_d_write_4(GICD_CTLR, 0x01);
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/* Activate IRQ 29, ie private timer IRQ*/
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gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
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}
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static int
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arm_gic_attach(device_t dev)
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{
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struct arm_gic_softc *sc;
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int i;
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uint32_t icciidr;
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if (arm_gic_sc)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Initialize mutex */
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mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
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/* Distributor Interface */
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sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
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sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
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/* CPU Interface */
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sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
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sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
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arm_gic_sc = sc;
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/* Disable interrupt forwarding to the CPU interface */
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gic_d_write_4(GICD_CTLR, 0x00);
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/* Get the number of interrupts */
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sc->nirqs = gic_d_read_4(GICD_TYPER);
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sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
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/* Set up function pointers */
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arm_post_filter = gic_post_filter;
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arm_config_irq = gic_config_irq;
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icciidr = gic_c_read_4(GICC_IIDR);
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device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x sc->nirqs %u\n",
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icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
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(icciidr & 0xfff), sc->nirqs);
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/* Set all global interrupts to be level triggered, active low. */
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for (i = 32; i < sc->nirqs; i += 16) {
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gic_d_write_4(GICD_ICFGR(i >> 4), 0x00000000);
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}
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/* Disable all interrupts. */
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for (i = 32; i < sc->nirqs; i += 32) {
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gic_d_write_4(GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
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}
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for (i = 0; i < sc->nirqs; i += 4) {
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gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
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gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
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}
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/* Set all the interrupts to be in Group 0 (secure) */
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for (i = 0; i < sc->nirqs; i += 32) {
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gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
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}
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/* Enable CPU interface */
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gic_c_write_4(GICC_CTLR, 1);
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/* Set priority mask register. */
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gic_c_write_4(GICC_PMR, 0xff);
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/* Enable interrupt distribution */
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gic_d_write_4(GICD_CTLR, 0x01);
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return (0);
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}
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static device_method_t arm_gic_methods[] = {
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DEVMETHOD(device_probe, arm_gic_probe),
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DEVMETHOD(device_attach, arm_gic_attach),
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{ 0, 0 }
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};
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static driver_t arm_gic_driver = {
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"gic",
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arm_gic_methods,
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sizeof(struct arm_gic_softc),
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};
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static devclass_t arm_gic_devclass;
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DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0);
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static void
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gic_post_filter(void *arg)
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{
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uintptr_t irq = (uintptr_t) arg;
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gic_c_write_4(GICC_EOIR, irq);
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}
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int
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arm_get_next_irq(int last_irq)
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{
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uint32_t active_irq;
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active_irq = gic_c_read_4(GICC_IAR);
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/*
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* Immediatly EOIR the SGIs, because doing so requires the other
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* bits (ie CPU number), not just the IRQ number, and we do not
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* have this information later.
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*/
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if ((active_irq & 0x3ff) < 16)
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gic_c_write_4(GICC_EOIR, active_irq);
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active_irq &= 0x3FF;
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if (active_irq == 0x3FF) {
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if (last_irq == -1)
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printf("Spurious interrupt detected [0x%08x]\n", active_irq);
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return -1;
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}
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return active_irq;
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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gic_d_write_4(GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
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gic_c_write_4(GICC_EOIR, nb);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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gic_d_write_4(GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
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}
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static int
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gic_config_irq(int irq, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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uint32_t reg;
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uint32_t mask;
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/* Function is public-accessible, so validate input arguments */
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if ((irq < 0) || (irq >= arm_gic_sc->nirqs))
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goto invalid_args;
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if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
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(trig != INTR_TRIGGER_CONFORM))
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goto invalid_args;
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if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) &&
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(pol != INTR_POLARITY_CONFORM))
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goto invalid_args;
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mtx_lock_spin(&arm_gic_sc->mutex);
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reg = gic_d_read_4(GICD_ICFGR(irq >> 4));
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mask = (reg >> 2*(irq % 16)) & 0x3;
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if (pol == INTR_POLARITY_LOW) {
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mask &= ~GICD_ICFGR_POL_MASK;
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mask |= GICD_ICFGR_POL_LOW;
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} else if (pol == INTR_POLARITY_HIGH) {
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mask &= ~GICD_ICFGR_POL_MASK;
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mask |= GICD_ICFGR_POL_HIGH;
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}
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if (trig == INTR_TRIGGER_LEVEL) {
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mask &= ~GICD_ICFGR_TRIG_MASK;
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mask |= GICD_ICFGR_TRIG_LVL;
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} else if (trig == INTR_TRIGGER_EDGE) {
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mask &= ~GICD_ICFGR_TRIG_MASK;
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mask |= GICD_ICFGR_TRIG_EDGE;
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}
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/* Set mask */
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reg = reg & ~(0x3 << 2*(irq % 16));
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reg = reg | (mask << 2*(irq % 16));
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gic_d_write_4(GICD_ICFGR(irq >> 4), reg);
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mtx_unlock_spin(&arm_gic_sc->mutex);
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return (0);
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invalid_args:
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device_printf(arm_gic_sc->dev, "gic_config_irg, invalid parameters\n");
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return (EINVAL);
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}
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#ifdef SMP
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void
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pic_ipi_send(cpuset_t cpus, u_int ipi)
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{
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uint32_t val = 0, i;
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for (i = 0; i < MAXCPU; i++)
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if (CPU_ISSET(i, &cpus))
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val |= 1 << (16 + i);
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gic_d_write_4(GICD_SGIR(0), val | ipi);
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}
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int
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pic_ipi_get(int i)
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{
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if (i != -1) {
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/*
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* The intr code will automagically give the frame pointer
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* if the interrupt argument is 0.
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*/
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if ((unsigned int)i > 16)
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return (0);
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return (i);
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}
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return (0x3ff);
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}
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void
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pic_ipi_clear(int ipi)
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{
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}
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#endif
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