999 lines
32 KiB
C
999 lines
32 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300reg.h"
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#include "ar9300/ar9300phy.h"
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#include "ar9300/ar9300desc.h"
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#define TU_TO_USEC(_tu) ((_tu) << 10)
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#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
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/*
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* Update Tx FIFO trigger level.
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*
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* Set b_inc_trig_level to TRUE to increase the trigger level.
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* Set b_inc_trig_level to FALSE to decrease the trigger level.
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*
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* Returns TRUE if the trigger level was updated
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*/
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HAL_BOOL
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ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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u_int32_t txcfg, cur_level, new_level;
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HAL_INT omask;
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if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
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b_inc_trig_level)
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{
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return AH_FALSE;
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}
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/*
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* Disable interrupts while futzing with the fifo level.
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*/
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omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0);
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txcfg = OS_REG_READ(ah, AR_TXCFG);
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cur_level = MS(txcfg, AR_FTRIG);
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new_level = cur_level;
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if (b_inc_trig_level) { /* increase the trigger level */
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if (cur_level < MAX_TX_FIFO_THRESHOLD) {
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new_level++;
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}
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} else if (cur_level > MIN_TX_FIFO_THRESHOLD) {
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new_level--;
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}
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if (new_level != cur_level) {
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/* Update the trigger level */
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OS_REG_WRITE(ah,
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AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG));
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}
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/* re-enable chip interrupts */
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ar9300_set_interrupts(ah, omask, 0);
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AH9300(ah)->ah_tx_trig_level = new_level;
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return (new_level != cur_level);
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}
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/*
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* Returns the value of Tx Trigger Level
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*/
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u_int16_t
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ar9300_get_tx_trig_level(struct ath_hal *ah)
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{
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return (AH9300(ah)->ah_tx_trig_level);
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}
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/*
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* Set the properties of the tx queue with the parameters
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* from q_info.
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*/
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HAL_BOOL
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ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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if (q >= p_cap->halTotalQueues) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
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return AH_FALSE;
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}
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return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
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}
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/*
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* Return the properties for the specified tx queue.
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*/
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HAL_BOOL
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ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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if (q >= p_cap->halTotalQueues) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
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return AH_FALSE;
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}
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return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
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}
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enum {
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AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1,
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AH_TX_QUEUE_MINUS_OFFSET_CAB = 2,
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AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3,
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AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4,
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};
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/*
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* Allocate and initialize a tx DCU/QCU combination.
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*/
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int
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ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
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const HAL_TXQ_INFO *q_info)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_TX_QUEUE_INFO *qi;
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HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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int q;
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/* XXX move queue assignment to driver */
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switch (type) {
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case HAL_TX_QUEUE_BEACON:
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/* highest priority */
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q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
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break;
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case HAL_TX_QUEUE_CAB:
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/* next highest priority */
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q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
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break;
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case HAL_TX_QUEUE_UAPSD:
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q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
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break;
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case HAL_TX_QUEUE_PAPRD:
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q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
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break;
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case HAL_TX_QUEUE_DATA:
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/*
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* don't infringe on top 4 queues, reserved for:
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* beacon, CAB, UAPSD, PAPRD
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*/
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for (q = 0;
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q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
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q++)
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{
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if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) {
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break;
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}
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}
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if (q == p_cap->halTotalQueues - 3) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE,
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"%s: no available tx queue\n", __func__);
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return -1;
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}
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_QUEUE,
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"%s: bad tx queue type %u\n", __func__, type);
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return -1;
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}
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE,
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"%s: tx queue %u already active\n", __func__, q);
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return -1;
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}
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OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
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qi->tqi_type = type;
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if (q_info == AH_NULL) {
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/* by default enable OK+ERR+DESC+URN interrupts */
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qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
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| HAL_TXQ_TXERRINT_ENABLE
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| HAL_TXQ_TXDESCINT_ENABLE
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| HAL_TXQ_TXURNINT_ENABLE;
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qi->tqi_aifs = INIT_AIFS;
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qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
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qi->tqi_cwmax = INIT_CWMAX;
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qi->tqi_shretry = INIT_SH_RETRY;
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qi->tqi_lgretry = INIT_LG_RETRY;
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qi->tqi_physCompBuf = 0;
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} else {
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qi->tqi_physCompBuf = q_info->tqi_compBuf;
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(void) ar9300_set_tx_queue_props(ah, q, q_info);
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}
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/* NB: must be followed by ar9300_reset_tx_queue */
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return q;
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}
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/*
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* Update the h/w interrupt registers to reflect a tx q's configuration.
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*/
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static void
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set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
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"%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n",
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__func__,
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ahp->ah_tx_ok_interrupt_mask,
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ahp->ah_tx_err_interrupt_mask,
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ahp->ah_tx_eol_interrupt_mask,
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ahp->ah_tx_urn_interrupt_mask);
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OS_REG_WRITE(ah, AR_IMR_S0,
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SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK));
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OS_REG_WRITE(ah, AR_IMR_S1,
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SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR)
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| SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
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OS_REG_RMW_FIELD(ah,
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AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask);
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ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
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}
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/*
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* Free a tx DCU/QCU combination.
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*/
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HAL_BOOL
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ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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HAL_TX_QUEUE_INFO *qi;
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if (q >= p_cap->halTotalQueues) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
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return AH_FALSE;
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}
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q);
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qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
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ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
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ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
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ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
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ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
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set_tx_q_interrupts(ah, qi);
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return AH_TRUE;
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}
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/*
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* Set the retry, aifs, cwmin/max, ready_time regs for specified queue
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* Assumes:
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* phw_channel has been set to point to the current channel
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*/
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HAL_BOOL
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ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_9300 *ahp = AH9300(ah);
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// struct ath_hal_private *ap = AH_PRIVATE(ah);
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HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
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const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
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HAL_TX_QUEUE_INFO *qi;
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u_int32_t cw_min, chan_cw_min, value;
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uint32_t qmisc, dmisc;
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if (q >= p_cap->halTotalQueues) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q);
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return AH_TRUE; /* XXX??? */
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}
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HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q);
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if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
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/*
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* Select cwmin according to channel type.
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* NB: chan can be NULL during attach
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*/
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if (chan && IEEE80211_IS_CHAN_B(chan)) {
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chan_cw_min = INIT_CWMIN_11B;
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} else {
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chan_cw_min = INIT_CWMIN;
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}
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/* make sure that the CWmin is of the form (2^n - 1) */
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for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {}
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} else {
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cw_min = qi->tqi_cwmin;
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}
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/* set cw_min/Max and AIFS values */
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if (q > 3 || (!AH9300(ah)->ah_fccaifs))
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/* values should not be overwritten if domain is FCC and manual rate
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less than 24Mb is set, this check is making sure this */
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{
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OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN)
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| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
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| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
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}
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/* Set retry limit values */
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OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
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SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
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SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
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SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
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/* enable early termination on the QCU */
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qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ;
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/* enable DCU to wait for next fragment from QCU */
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if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) {
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/* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff
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* threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */
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dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1;
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} else {
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dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2;
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}
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/* multiqueue support */
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if (qi->tqi_cbrPeriod) {
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OS_REG_WRITE(ah,
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AR_QCBRCFG(q),
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SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
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SM(qi->tqi_cbrOverflowLimit,
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AR_Q_CBRCFG_OVF_THRESH));
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qmisc |= AR_Q_MISC_FSP_CBR |
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(qi->tqi_cbrOverflowLimit ?
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AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0);
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}
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if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
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OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
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SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
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AR_Q_RDYTIMECFG_EN);
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}
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OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
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(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
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if (qi->tqi_readyTime &&
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(qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
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qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY;
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if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
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qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED;
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if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) {
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/*
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* These are meangingful only when not scheduled asap.
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*/
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if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
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qmisc |= AR_Q_MISC_CBR_INCR_DIS0;
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else
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qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
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if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
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qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
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else
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qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
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}
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if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
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dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
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if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
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dmisc |= AR_D_MISC_FRAG_BKOFF_EN;
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if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
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dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
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AR_D_MISC_ARB_LOCKOUT_CNTRL);
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else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
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dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR,
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AR_D_MISC_ARB_LOCKOUT_CNTRL);
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if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
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dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE,
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AR_D_MISC_VIR_COL_HANDLING);
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if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
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dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS;
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_BEACON: /* beacon frames */
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qmisc |= AR_Q_MISC_FSP_DBA_GATED
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| AR_Q_MISC_BEACON_USE
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| AR_Q_MISC_CBR_INCR_DIS1;
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dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
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AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
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| AR_D_MISC_BEACON_USE
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| AR_D_MISC_POST_FR_BKOFF_DIS;
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/* XXX cwmin and cwmax should be 0 for beacon queue */
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if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) {
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OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
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| SM(0, AR_D_LCL_IFS_CWMAX)
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| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
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}
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break;
|
|
case HAL_TX_QUEUE_CAB: /* CAB frames */
|
|
/*
|
|
* No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
|
|
* bug #6079. There is an issue with the CAB Queue
|
|
* not properly refreshing the Tx descriptor if
|
|
* the TXE clear setting is used.
|
|
*/
|
|
qmisc |= AR_Q_MISC_FSP_DBA_GATED
|
|
| AR_Q_MISC_CBR_INCR_DIS1
|
|
| AR_Q_MISC_CBR_INCR_DIS0;
|
|
|
|
if (qi->tqi_readyTime) {
|
|
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
|
|
SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
|
|
AR_Q_RDYTIMECFG_EN);
|
|
} else {
|
|
|
|
value = (ahp->ah_beaconInterval * 50 / 100)
|
|
- ah->ah_config.ah_additional_swba_backoff
|
|
- ah->ah_config.ah_sw_beacon_response_time
|
|
+ ah->ah_config.ah_dma_beacon_response_time;
|
|
/*
|
|
* XXX Ensure it isn't too low - nothing lower
|
|
* XXX than 10 TU
|
|
*/
|
|
if (value < 10)
|
|
value = 10;
|
|
if (value < 0)
|
|
value = 10;
|
|
HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
|
|
"%s: defaulting to rdytime = %d uS\n",
|
|
__func__, value);
|
|
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
|
|
SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_DURATION) |
|
|
AR_Q_RDYTIMECFG_EN);
|
|
}
|
|
dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
|
|
AR_D_MISC_ARB_LOCKOUT_CNTRL);
|
|
break;
|
|
case HAL_TX_QUEUE_PSPOLL:
|
|
/*
|
|
* We may configure ps_poll QCU to be TIM-gated in the
|
|
* future; TIM_GATED bit is not enabled currently because
|
|
* of a hardware problem in Oahu that overshoots the TIM
|
|
* bitmap in beacon and may find matching associd bit in
|
|
* non-TIM elements and send PS-poll PS poll processing
|
|
* will be done in software
|
|
*/
|
|
qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
|
|
break;
|
|
case HAL_TX_QUEUE_UAPSD:
|
|
dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
|
|
break;
|
|
default: /* NB: silence compiler */
|
|
break;
|
|
}
|
|
|
|
#ifndef AH_DISABLE_WME
|
|
/*
|
|
* Yes, this is a hack and not the right way to do it, but
|
|
* it does get the lockout bits and backoff set for the
|
|
* high-pri WME queues for testing. We need to either extend
|
|
* the meaning of queue_info->mode, or create something like
|
|
* queue_info->dcumode.
|
|
*/
|
|
if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
|
|
dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
|
|
AR_D_MISC_ARB_LOCKOUT_CNTRL) |
|
|
AR_D_MISC_POST_FR_BKOFF_DIS;
|
|
}
|
|
#endif
|
|
|
|
OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
|
|
OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
|
|
OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
|
|
|
|
/*
|
|
* Always update the secondary interrupt mask registers - this
|
|
* could be a new queue getting enabled in a running system or
|
|
* hw getting re-initialized during a reset!
|
|
*
|
|
* Since we don't differentiate between tx interrupts corresponding
|
|
* to individual queues - secondary tx mask regs are always unmasked;
|
|
* tx interrupts are enabled/disabled for all queues collectively
|
|
* using the primary mask reg
|
|
*/
|
|
if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
|
|
ahp->ah_tx_ok_interrupt_mask |= (1 << q);
|
|
} else {
|
|
ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
|
|
}
|
|
if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
|
|
ahp->ah_tx_err_interrupt_mask |= (1 << q);
|
|
} else {
|
|
ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
|
|
}
|
|
if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
|
|
ahp->ah_tx_eol_interrupt_mask |= (1 << q);
|
|
} else {
|
|
ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
|
|
}
|
|
if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
|
|
ahp->ah_tx_urn_interrupt_mask |= (1 << q);
|
|
} else {
|
|
ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
|
|
}
|
|
set_tx_q_interrupts(ah, qi);
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Get the TXDP for the specified queue
|
|
*/
|
|
u_int32_t
|
|
ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
|
|
{
|
|
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
|
|
return OS_REG_READ(ah, AR_QTXDP(q));
|
|
}
|
|
|
|
/*
|
|
* Set the tx_dp for the specified queue
|
|
*/
|
|
HAL_BOOL
|
|
ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
|
|
{
|
|
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
|
|
HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
HALASSERT(txdp != 0);
|
|
|
|
OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Transmit Enable is read-only now
|
|
*/
|
|
HAL_BOOL
|
|
ar9300_start_tx_dma(struct ath_hal *ah, u_int q)
|
|
{
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Return the number of pending frames or 0 if the specified
|
|
* queue is stopped.
|
|
*/
|
|
u_int32_t
|
|
ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
|
|
{
|
|
u_int32_t npend;
|
|
|
|
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
|
|
|
|
npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
|
|
if (npend == 0) {
|
|
/*
|
|
* Pending frame count (PFC) can momentarily go to zero
|
|
* while TXE remains asserted. In other words a PFC of
|
|
* zero is not sufficient to say that the queue has stopped.
|
|
*/
|
|
if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) {
|
|
npend = 1; /* arbitrarily return 1 */
|
|
}
|
|
}
|
|
#ifdef DEBUG
|
|
if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
|
|
if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n");
|
|
/* Clear the ready_time shutdown status bits */
|
|
OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
|
|
}
|
|
}
|
|
#endif
|
|
HALASSERT((npend == 0) ||
|
|
(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE));
|
|
|
|
return npend;
|
|
}
|
|
|
|
/*
|
|
* Stop transmit on the specified queue
|
|
*/
|
|
HAL_BOOL
|
|
ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout)
|
|
{
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
|
|
/*
|
|
* If we call abort txdma instead, no need to stop RX.
|
|
* Otherwise, the RX logic might not be restarted properly.
|
|
*/
|
|
ahp->ah_abort_txdma_norx = AH_FALSE;
|
|
|
|
/*
|
|
* Directly call abort. It is better, hardware-wise, to stop all
|
|
* queues at once than individual ones.
|
|
*/
|
|
return ar9300_abort_tx_dma(ah);
|
|
|
|
#if 0
|
|
#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
|
|
#define AH_TIME_QUANTUM 100 /* usec */
|
|
u_int wait;
|
|
|
|
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
|
|
|
|
HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
|
|
if (timeout == 0) {
|
|
timeout = AH_TX_STOP_DMA_TIMEOUT;
|
|
}
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
|
|
|
|
for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
|
|
if (ar9300_num_tx_pending(ah, q) == 0) {
|
|
break;
|
|
}
|
|
OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
|
|
}
|
|
|
|
#ifdef AH_DEBUG
|
|
if (wait == 0) {
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
|
|
__func__,
|
|
OS_REG_READ(ah, AR_QSTS(q)),
|
|
OS_REG_READ(ah, AR_Q_TXE),
|
|
OS_REG_READ(ah, AR_Q_TXD),
|
|
OS_REG_READ(ah, AR_QCBRCFG(q)));
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
|
|
__func__,
|
|
OS_REG_READ(ah, AR_QMISC(q)),
|
|
OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
|
|
OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
|
|
}
|
|
#endif /* AH_DEBUG */
|
|
|
|
/* 2413+ and up can kill packets at the PCU level */
|
|
if (ar9300_num_tx_pending(ah, q)) {
|
|
u_int32_t tsf_low, j;
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
|
|
__func__, ar9300_num_tx_pending(ah, q), q);
|
|
|
|
/* Kill last PCU Tx Frame */
|
|
/* TODO - save off and restore current values of Q1/Q2? */
|
|
for (j = 0; j < 2; j++) {
|
|
tsf_low = OS_REG_READ(ah, AR_TSF_L32);
|
|
OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
|
|
OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
|
|
OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
|
|
OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
|
|
|
|
if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
|
|
break;
|
|
}
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: TSF have moved while trying to set "
|
|
"quiet time TSF: 0x%08x\n",
|
|
__func__, tsf_low);
|
|
/* TSF shouldn't count twice or reg access is taking forever */
|
|
HALASSERT(j < 1);
|
|
}
|
|
|
|
OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
|
|
|
|
/* Allow the quiet mechanism to do its work */
|
|
OS_DELAY(200);
|
|
OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
|
|
|
|
/* Verify all transmit is dead */
|
|
wait = timeout / AH_TIME_QUANTUM;
|
|
while (ar9300_num_tx_pending(ah, q)) {
|
|
if ((--wait) == 0) {
|
|
HALDEBUG(ah, HAL_DEBUG_TX,
|
|
"%s: Failed to stop Tx DMA in %d msec "
|
|
"after killing last frame\n",
|
|
__func__, timeout / 1000);
|
|
break;
|
|
}
|
|
OS_DELAY(AH_TIME_QUANTUM);
|
|
}
|
|
|
|
OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
|
|
}
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 0);
|
|
return (wait != 0);
|
|
|
|
#undef AH_TX_STOP_DMA_TIMEOUT
|
|
#undef AH_TIME_QUANTUM
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Really Stop transmit on the specified queue
|
|
*/
|
|
HAL_BOOL
|
|
ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout)
|
|
{
|
|
#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */
|
|
#define AH_TIME_QUANTUM 100 /* usec */
|
|
u_int wait;
|
|
|
|
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
|
|
|
|
HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
|
|
if (timeout == 0) {
|
|
timeout = AH_TX_STOP_DMA_TIMEOUT;
|
|
}
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
|
|
|
|
for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) {
|
|
if (ar9300_num_tx_pending(ah, q) == 0) {
|
|
break;
|
|
}
|
|
OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */
|
|
}
|
|
|
|
#ifdef AH_DEBUG
|
|
if (wait == 0) {
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n",
|
|
__func__,
|
|
OS_REG_READ(ah, AR_QSTS(q)),
|
|
OS_REG_READ(ah, AR_Q_TXE),
|
|
OS_REG_READ(ah, AR_Q_TXD),
|
|
OS_REG_READ(ah, AR_QCBRCFG(q)));
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
|
|
__func__,
|
|
OS_REG_READ(ah, AR_QMISC(q)),
|
|
OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
|
|
OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
|
|
}
|
|
#endif /* AH_DEBUG */
|
|
|
|
/* 2413+ and up can kill packets at the PCU level */
|
|
if (ar9300_num_tx_pending(ah, q)) {
|
|
u_int32_t tsf_low, j;
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n",
|
|
__func__, ar9300_num_tx_pending(ah, q), q);
|
|
|
|
/* Kill last PCU Tx Frame */
|
|
/* TODO - save off and restore current values of Q1/Q2? */
|
|
for (j = 0; j < 2; j++) {
|
|
tsf_low = OS_REG_READ(ah, AR_TSF_L32);
|
|
OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
|
|
OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
|
|
OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10);
|
|
OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
|
|
|
|
if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) {
|
|
break;
|
|
}
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: TSF have moved while trying to set "
|
|
"quiet time TSF: 0x%08x\n",
|
|
__func__, tsf_low);
|
|
/* TSF shouldn't count twice or reg access is taking forever */
|
|
HALASSERT(j < 1);
|
|
}
|
|
|
|
OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
|
|
|
|
/* Allow the quiet mechanism to do its work */
|
|
OS_DELAY(200);
|
|
OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
|
|
|
|
/* Verify all transmit is dead */
|
|
wait = timeout / AH_TIME_QUANTUM;
|
|
while (ar9300_num_tx_pending(ah, q)) {
|
|
if ((--wait) == 0) {
|
|
HALDEBUG(ah, HAL_DEBUG_TX,
|
|
"%s: Failed to stop Tx DMA in %d msec "
|
|
"after killing last frame\n",
|
|
__func__, timeout / 1000);
|
|
break;
|
|
}
|
|
OS_DELAY(AH_TIME_QUANTUM);
|
|
}
|
|
|
|
OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
|
|
}
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 0);
|
|
return (wait != 0);
|
|
|
|
#undef AH_TX_STOP_DMA_TIMEOUT
|
|
#undef AH_TIME_QUANTUM
|
|
}
|
|
|
|
/*
|
|
* Abort transmit on all queues
|
|
*/
|
|
#define AR9300_ABORT_LOOPS 1000
|
|
#define AR9300_ABORT_WAIT 5
|
|
#define NEXT_TBTT_NOW 10
|
|
HAL_BOOL
|
|
ar9300_abort_tx_dma(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
int i, q;
|
|
u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba;
|
|
HAL_BOOL stopped;
|
|
HAL_BOOL status = AH_TRUE;
|
|
|
|
if (ahp->ah_abort_txdma_norx) {
|
|
/*
|
|
* First of all, make sure RX has been stopped
|
|
*/
|
|
if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
|
|
/* Need to stop RX DMA before reset otherwise chip might hang */
|
|
stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
|
|
ar9300_set_rx_filter(ah, 0);
|
|
stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
|
|
if (!stopped) {
|
|
/*
|
|
* During the transition from full sleep to reset,
|
|
* recv DMA regs are not available to be read
|
|
*/
|
|
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
|
|
"%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__);
|
|
//We still continue to stop TX dma
|
|
//return AH_FALSE;
|
|
}
|
|
} else {
|
|
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
|
|
"%s[%d]: Chip is already in full sleep\n", __func__, __LINE__);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* set txd on all queues
|
|
*/
|
|
OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
|
|
|
|
/*
|
|
* set tx abort bits (also disable rx)
|
|
*/
|
|
OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
|
|
/* Add a new receipe from K31 code */
|
|
OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
|
|
AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
|
|
/* beacon Q flush */
|
|
nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER);
|
|
nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT);
|
|
//printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt);
|
|
tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32);
|
|
tbtt = tsf_tbtt + NEXT_TBTT_NOW;
|
|
dba = tsf_tbtt;
|
|
OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba);
|
|
OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt);
|
|
OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
|
|
|
|
/*
|
|
* Let TXE (all queues) clear before waiting for any pending frames
|
|
* This is needed before starting the RF_BUS GRANT sequence other wise causes kernel
|
|
* panic
|
|
*/
|
|
for(i = 0; i < AR9300_ABORT_LOOPS; i++) {
|
|
if(OS_REG_READ(ah, AR_Q_TXE) == 0) {
|
|
break;
|
|
}
|
|
OS_DELAY(AR9300_ABORT_WAIT);
|
|
}
|
|
if (i == AR9300_ABORT_LOOPS) {
|
|
HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n",
|
|
__func__, __LINE__);
|
|
}
|
|
|
|
/*
|
|
* wait on all tx queues
|
|
* This need to be checked in the last to gain extra 50 usec. on avg.
|
|
* Currently checked first since we dont have a previous channel information currently.
|
|
* Which is needed to revert the rf changes.
|
|
*/
|
|
for (q = AR_NUM_QCU - 1; q >= 0; q--) {
|
|
for (i = 0; i < AR9300_ABORT_LOOPS; i++) {
|
|
if (!(ar9300_num_tx_pending(ah, q))) {
|
|
break;
|
|
}
|
|
OS_DELAY(AR9300_ABORT_WAIT);
|
|
}
|
|
if (i == AR9300_ABORT_LOOPS) {
|
|
status = AH_FALSE;
|
|
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
|
|
"ABORT LOOP finsihsed for Q: %d, num_pending: %d \n",
|
|
q, ar9300_num_tx_pending(ah, q));
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
/* Updating the beacon alert register with correct value */
|
|
OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba);
|
|
OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt);
|
|
|
|
exit:
|
|
/*
|
|
* clear tx abort bits
|
|
*/
|
|
OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
|
|
/* Added a new receipe from K31 code */
|
|
OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS |
|
|
AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);
|
|
OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
|
|
|
|
/*
|
|
* clear txd
|
|
*/
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 0);
|
|
|
|
ahp->ah_abort_txdma_norx = AH_TRUE;
|
|
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Determine which tx queues need interrupt servicing.
|
|
*/
|
|
void
|
|
ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs)
|
|
{
|
|
HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
|
|
"ar9300_get_tx_intr_queue: Should not be called\n");
|
|
#if 0
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
*txqs &= ahp->ah_intr_txqs;
|
|
ahp->ah_intr_txqs &= ~(*txqs);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
ar9300_reset_tx_status_ring(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
|
|
ahp->ts_tail = 0;
|
|
|
|
/* Zero out the status descriptors */
|
|
OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs));
|
|
HALDEBUG(ah, HAL_DEBUG_QUEUE,
|
|
"%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__,
|
|
ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size);
|
|
|
|
OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start);
|
|
OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end);
|
|
}
|
|
|
|
void
|
|
ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
|
|
u_int32_t ts_paddr_start, u_int16_t size)
|
|
{
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
|
|
ahp->ts_paddr_start = ts_paddr_start;
|
|
ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs));
|
|
ahp->ts_size = size;
|
|
ahp->ts_ring = (struct ar9300_txs *)ts_start;
|
|
|
|
ar9300_reset_tx_status_ring(ah);
|
|
}
|