990 lines
28 KiB
C
990 lines
28 KiB
C
/*-
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* Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#ifdef __alpha__
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#include <machine/md_var.h>
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#endif
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#include <sys/rman.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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/* device structures */
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struct ata_pci_controller {
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struct resource *bmio;
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int bmaddr;
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struct resource *irq;
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int irqcnt;
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int lock;
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};
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/* misc defines */
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#define IOMASK 0xfffffffc
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#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
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#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
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(pci_get_progif(dev) & 0x05) != 0x05)
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int
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ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
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{
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device_t *children;
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int nchildren, i;
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if (device_get_children(device_get_parent(dev), &children, &nchildren))
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return 0;
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == devid &&
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pci_get_revid(children[i]) >= revid) {
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free(children, M_TEMP);
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return 1;
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}
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}
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free(children, M_TEMP);
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return 0;
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}
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static void
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ata_via_southbridge_fixup(device_t dev)
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{
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device_t *children;
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int nchildren, i;
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if (device_get_children(device_get_parent(dev), &children, &nchildren))
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return;
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
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pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
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pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
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pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
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u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
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if ((reg76 & 0xf0) != 0xd0) {
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device_printf(dev,
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"Correcting VIA config for southbridge data corruption bug\n");
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pci_write_config(children[i], 0x75, 0x80, 1);
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pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
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}
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break;
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}
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}
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free(children, M_TEMP);
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}
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static const char *
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ata_pci_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_STORAGE)
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return NULL;
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switch (pci_get_devid(dev)) {
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/* supported chipsets */
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case 0x12308086:
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return "Intel PIIX ATA controller";
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case 0x70108086:
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return "Intel PIIX3 ATA controller";
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case 0x71118086:
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case 0x71998086:
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case 0x84ca8086:
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return "Intel PIIX4 ATA33 controller";
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case 0x24218086:
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return "Intel ICH0 ATA33 controller";
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case 0x24118086:
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case 0x76018086:
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return "Intel ICH ATA66 controller";
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case 0x244a8086:
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case 0x244b8086:
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return "Intel ICH2 ATA100 controller";
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case 0x248a8086:
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case 0x248b8086:
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return "Intel ICH3 ATA100 controller";
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case 0x24cb8086:
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return "Intel ICH4 ATA100 controller";
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case 0x522910b9:
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if (pci_get_revid(dev) >= 0xc4)
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return "AcerLabs Aladdin ATA100 controller";
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else if (pci_get_revid(dev) >= 0xc2)
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return "AcerLabs Aladdin ATA66 controller";
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else if (pci_get_revid(dev) >= 0x20)
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return "AcerLabs Aladdin ATA33 controller";
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else
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return "AcerLabs Aladdin ATA controller";
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case 0x05711106:
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if (ata_find_dev(dev, 0x05861106, 0x02))
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return "VIA 82C586 ATA33 controller";
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if (ata_find_dev(dev, 0x05861106, 0))
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return "VIA 82C586 ATA controller";
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if (ata_find_dev(dev, 0x05961106, 0x12))
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return "VIA 82C596 ATA66 controller";
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if (ata_find_dev(dev, 0x05961106, 0))
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return "VIA 82C596 ATA33 controller";
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if (ata_find_dev(dev, 0x06861106, 0x40))
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return "VIA 82C686 ATA100 controller";
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if (ata_find_dev(dev, 0x06861106, 0x10))
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return "VIA 82C686 ATA66 controller";
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if (ata_find_dev(dev, 0x06861106, 0))
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return "VIA 82C686 ATA33 controller";
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if (ata_find_dev(dev, 0x82311106, 0))
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return "VIA 8231 ATA100 controller";
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if (ata_find_dev(dev, 0x30741106, 0) ||
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ata_find_dev(dev, 0x31091106, 0))
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return "VIA 8233 ATA100 controller";
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if (ata_find_dev(dev, 0x31471106, 0))
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return "VIA 8233 ATA133 controller";
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if (ata_find_dev(dev, 0x31771106, 0))
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return "VIA 8235 ATA133 controller";
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return "VIA Apollo ATA controller";
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case 0x55131039:
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if (ata_find_dev(dev, 0x06301039, 0x30) ||
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ata_find_dev(dev, 0x06331039, 0) ||
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ata_find_dev(dev, 0x06351039, 0) ||
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ata_find_dev(dev, 0x06401039, 0) ||
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ata_find_dev(dev, 0x06451039, 0) ||
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ata_find_dev(dev, 0x06501039, 0) ||
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ata_find_dev(dev, 0x07301039, 0) ||
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ata_find_dev(dev, 0x07331039, 0) ||
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ata_find_dev(dev, 0x07351039, 0) ||
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ata_find_dev(dev, 0x07401039, 0) ||
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ata_find_dev(dev, 0x07451039, 0) ||
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ata_find_dev(dev, 0x07501039, 0))
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return "SiS 5591 ATA100 controller";
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else if (ata_find_dev(dev, 0x05301039, 0) ||
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ata_find_dev(dev, 0x05401039, 0) ||
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ata_find_dev(dev, 0x06201039, 0) ||
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ata_find_dev(dev, 0x06301039, 0))
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return "SiS 5591 ATA66 controller";
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else
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return "SiS 5591 ATA33 controller";
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case 0x06801095:
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return "Sil 0680 ATA133 controller";
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case 0x06491095:
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return "CMD 649 ATA100 controller";
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case 0x06481095:
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return "CMD 648 ATA66 controller";
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case 0x06461095:
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return "CMD 646 ATA controller";
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case 0xc6931080:
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if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
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return "Cypress 82C693 ATA controller";
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return NULL;
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case 0x01021078:
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return "Cyrix 5530 ATA33 controller";
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case 0x74091022:
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return "AMD 756 ATA66 controller";
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case 0x74111022:
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return "AMD 766 ATA100 controller";
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case 0x74411022:
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return "AMD 768 ATA100 controller";
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case 0x01bc10de:
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return "nVidia nForce ATA100 controller";
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case 0x006510de:
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return "nVidia nForce ATA133 controller";
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case 0x02111166:
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return "ServerWorks ROSB4 ATA33 controller";
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case 0x02121166:
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if (pci_get_revid(dev) >= 0x92)
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return "ServerWorks CSB5 ATA100 controller";
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else
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return "ServerWorks CSB5 ATA66 controller";
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case 0x02131166:
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return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
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case 0x02171166:
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return "ServerWorks CSB6 ATA66 controller (channel 2)";
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case 0x4d33105a:
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return "Promise ATA33 controller";
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case 0x0d38105a:
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case 0x4d38105a:
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return "Promise ATA66 controller";
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case 0x0d30105a:
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case 0x4d30105a:
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return "Promise ATA100 controller";
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case 0x4d68105a:
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case 0x6268105a:
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{
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uintptr_t devid = 0;
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/* test if we are behind the right type of bridge */
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if (!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
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GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
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devid == 0x00221011 &&
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pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
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static long start = 0, end = 0;
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/* we belive we are on a TX4, now do our (simple) magic */
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if (pci_get_slot(dev) == 1) {
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bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
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return "Promise TX4 ATA100 controller (channel 0+1)";
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}
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else if (pci_get_slot(dev) == 2 && start && end) {
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bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
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start = end = 0;
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return "Promise TX4 ATA100 controller (channel 2+3)";
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}
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else
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start = end = 0;
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}
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}
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return "Promise TX2 ATA100 controller";
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case 0x1275105a:
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case 0x5275105a:
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case 0x7275105a:
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{
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uintptr_t devid = 0;
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/* if we are on a SuperTrak SX6000 dont attach */
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if (!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
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GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
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devid == 0x09628086 &&
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pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE)
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break;
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}
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/* FALLTHROUGH */
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case 0x4d69105a:
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case 0x6269105a:
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return "Promise TX2 ATA133 controller";
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case 0x00041103:
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switch (pci_get_revid(dev)) {
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case 0x00:
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case 0x01:
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return "HighPoint HPT366 ATA66 controller";
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case 0x02:
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return "HighPoint HPT368 ATA66 controller";
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case 0x03:
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case 0x04:
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return "HighPoint HPT370 ATA100 controller";
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case 0x05:
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return "HighPoint HPT372 ATA133 controller";
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}
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return NULL;
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case 0x00051103:
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switch (pci_get_revid(dev)) {
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case 0x01:
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return "HighPoint HPT372 ATA133 controller";
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}
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return NULL;
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case 0x00081103:
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switch (pci_get_revid(dev)) {
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case 0x07:
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if (pci_get_function(dev) == 0)
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return "HighPoint HPT374 ATA133 controller (channel 0+1)";
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if (pci_get_function(dev) == 1)
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return "HighPoint HPT374 ATA133 controller (channel 2+3)";
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return "HighPoint HPT374 ATA133 controller";
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}
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return NULL;
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case 0x00051191:
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return "Acard ATP850 ATA-33 controller";
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case 0x00061191:
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case 0x00071191:
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return "Acard ATP860 ATA-66 controller";
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case 0x00081191:
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case 0x00091191:
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return "Acard ATP865 ATA-133 controller";
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case 0x000116ca:
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return "Cenatek Rocket Drive controller";
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/* unsupported but known chipsets, generic DMA only */
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case 0x10001042:
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case 0x10011042:
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return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
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case 0x06401095:
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return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
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/* unknown chipsets, try generic DMA if it seems possible */
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default:
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if (pci_get_class(dev) == PCIC_STORAGE &&
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(pci_get_subclass(dev) == PCIS_STORAGE_IDE))
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return "Generic PCI ATA controller";
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}
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return NULL;
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}
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static int
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ata_pci_probe(device_t dev)
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{
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const char *desc = ata_pci_match(dev);
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if (desc) {
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device_set_desc(dev, desc);
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return 0;
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}
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else
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return ENXIO;
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}
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static int
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ata_pci_add_child(device_t dev, int unit)
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{
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/* check if this is located at one of the std addresses */
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if (ATA_MASTERDEV(dev)) {
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if (!device_add_child(dev, "ata", unit))
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return ENOMEM;
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}
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else {
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if (!device_add_child(dev, "ata",
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devclass_find_free_unit(ata_devclass, 2)))
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return ENOMEM;
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}
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return 0;
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}
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static int
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ata_pci_attach(device_t dev)
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{
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struct ata_pci_controller *controller = device_get_softc(dev);
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u_int8_t class, subclass;
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u_int32_t type, cmd;
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int rid;
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/* set up vendor-specific stuff */
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type = pci_get_devid(dev);
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class = pci_get_class(dev);
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subclass = pci_get_subclass(dev);
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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if (!(cmd & PCIM_CMD_PORTEN)) {
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device_printf(dev, "ATA channel disabled by BIOS\n");
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return 0;
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}
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#ifdef __sparc64__
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if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
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pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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}
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#endif
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/* is busmastering supported ? */
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if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
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(PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
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/* is there a valid port range to connect to ? */
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rid = 0x20;
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controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
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0, ~0, 1, RF_ACTIVE);
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if (!controller->bmio)
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device_printf(dev, "Busmastering DMA not configured\n");
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}
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else
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device_printf(dev, "Busmastering DMA not supported\n");
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/* do extra chipset specific setups */
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switch (type) {
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case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */
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pci_write_config(dev, 0x53,
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(pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
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break;
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case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */
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case 0x4d30105a:
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case 0x0d38105a:
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case 0x4d38105a:
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ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
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/* FALLTHROUGH */
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case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
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ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
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break;
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case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */
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if (pci_get_revid(dev) < 2) { /* HPT366 */
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/* turn off interrupt prediction */
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pci_write_config(dev, 0x51,
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(pci_read_config(dev, 0x51, 1) & ~0x80), 1);
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break;
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}
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if (pci_get_revid(dev) < 5) { /* HPT368/370 */
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/* turn off interrupt prediction */
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pci_write_config(dev, 0x51,
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(pci_read_config(dev, 0x51, 1) & ~0x03), 1);
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pci_write_config(dev, 0x55,
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(pci_read_config(dev, 0x55, 1) & ~0x03), 1);
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/* turn on interrupts */
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pci_write_config(dev, 0x5a,
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(pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
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/* set clocks etc */
|
|
pci_write_config(dev, 0x5b, 0x22, 1);
|
|
break;
|
|
}
|
|
/* FALLTHROUGH */
|
|
|
|
case 0x00051103: /* HighPoint HPT372 default setup */
|
|
case 0x00081103: /* HighPoint HPT374 default setup */
|
|
/* turn off interrupt prediction */
|
|
pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
|
|
pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
|
|
|
|
/* turn on interrupts */
|
|
pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
|
|
|
|
/* set clocks etc */
|
|
pci_write_config(dev, 0x5b,
|
|
(pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
|
|
break;
|
|
|
|
case 0x05711106: /* VIA 82C586, '596, '686 default setup */
|
|
/* prepare for ATA-66 on the 82C686a and 82C596b */
|
|
if ((ata_find_dev(dev, 0x06861106, 0x10) &&
|
|
!ata_find_dev(dev, 0x06861106, 0x40)) ||
|
|
ata_find_dev(dev, 0x05961106, 0x12))
|
|
pci_write_config(dev, 0x50, 0x030b030b, 4);
|
|
|
|
/* the southbridge might need the data corruption fix */
|
|
if (ata_find_dev(dev, 0x06861106, 0x40) ||
|
|
ata_find_dev(dev, 0x82311106, 0x10))
|
|
ata_via_southbridge_fixup(dev);
|
|
/* FALLTHROUGH */
|
|
|
|
case 0x74091022: /* AMD 756 default setup */
|
|
case 0x74111022: /* AMD 766 default setup */
|
|
case 0x74411022: /* AMD 768 default setup */
|
|
case 0x01bc10de: /* nVIDIA nForce default setup */
|
|
/* set prefetch, postwrite */
|
|
pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
|
|
|
|
/* set fifo configuration half'n'half */
|
|
pci_write_config(dev, 0x43,
|
|
(pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
|
|
|
|
/* set status register read retry */
|
|
pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
|
|
|
|
/* set DMA read & end-of-sector fifo flush */
|
|
pci_write_config(dev, 0x46,
|
|
(pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
|
|
|
|
/* set sector size */
|
|
pci_write_config(dev, 0x60, DEV_BSIZE, 2);
|
|
pci_write_config(dev, 0x68, DEV_BSIZE, 2);
|
|
break;
|
|
|
|
case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
|
|
pci_write_config(dev, 0x64,
|
|
(pci_read_config(dev, 0x64, 4) & ~0x00002000) |
|
|
0x00004000, 4);
|
|
break;
|
|
|
|
case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
|
|
pci_write_config(dev, 0x5a,
|
|
(pci_read_config(dev, 0x5a, 1) & ~0x40) |
|
|
(pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
|
|
break;
|
|
|
|
case 0x06801095: /* Sil 0680 set ATA reference clock speed */
|
|
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
|
|
pci_write_config(dev, 0x8a,
|
|
(pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
|
|
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
|
|
device_printf(dev, "Sil 0680 could not set clock\n");
|
|
break;
|
|
|
|
case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
|
|
pci_write_config(dev, 0x71, 0x01, 1);
|
|
break;
|
|
|
|
case 0x10001042: /* RZ 100? known bad, no DMA */
|
|
case 0x10011042:
|
|
case 0x06401095: /* CMD 640 known bad, no DMA */
|
|
controller->bmio = NULL;
|
|
device_printf(dev, "Busmastering DMA disabled\n");
|
|
}
|
|
|
|
if (controller->bmio) {
|
|
controller->bmaddr = rman_get_start(controller->bmio);
|
|
BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, rid, controller->bmio);
|
|
controller->bmio = NULL;
|
|
}
|
|
controller->lock = -1;
|
|
|
|
/*
|
|
* the Cypress chip is a mess, it contains two ATA functions, but
|
|
* both channels are visible on the first one.
|
|
* simply ignore the second function for now, as the right
|
|
* solution (ignoring the second channel on the first function)
|
|
* doesn't work with the crappy ATA interrupt setup on the alpha.
|
|
*/
|
|
if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
|
|
return 0;
|
|
|
|
ata_pci_add_child(dev, 0);
|
|
|
|
if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
|
|
ata_pci_add_child(dev, 1);
|
|
|
|
return bus_generic_attach(dev);
|
|
}
|
|
|
|
static int
|
|
ata_pci_intr(struct ata_channel *ch)
|
|
{
|
|
u_int8_t dmastat;
|
|
|
|
/*
|
|
* since we might share the IRQ with another device, and in some
|
|
* cases with our twin channel, we only want to process interrupts
|
|
* that we know this channel generated.
|
|
*/
|
|
switch (ch->chiptype) {
|
|
case 0x00041103: /* HighPoint HPT366/368/370/372 */
|
|
case 0x00051103: /* HighPoint HPT372 */
|
|
case 0x00081103: /* HighPoint HPT374 */
|
|
if (((dmastat = ata_dmastatus(ch)) &
|
|
(ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
|
|
return 0;
|
|
ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
|
|
DELAY(1);
|
|
return 1;
|
|
|
|
case 0x06481095: /* CMD 648 */
|
|
case 0x06491095: /* CMD 649 */
|
|
if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
|
|
(ch->unit ? 0x08 : 0x04)))
|
|
return 0;
|
|
break;
|
|
|
|
case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
|
|
case 0x0d38105a: /* Promise Fasttrak 66 */
|
|
case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
|
|
case 0x0d30105a: /* Promise OEM ATA100 */
|
|
case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
|
|
if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
|
|
(ch->unit ? 0x00004000 : 0x00000400)))
|
|
return 0;
|
|
break;
|
|
|
|
case 0x4d68105a: /* Promise TX2 ATA100 */
|
|
case 0x6268105a: /* Promise TX2 ATA100 */
|
|
case 0x4d69105a: /* Promise TX2 ATA133 */
|
|
case 0x1275105a: /* Promise TX2 ATA133 */
|
|
case 0x5275105a: /* Promise TX2 ATA133 */
|
|
case 0x6269105a: /* Promise TX2 ATA133 */
|
|
case 0x7275105a: /* Promise TX2 ATA133 */
|
|
ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
|
|
if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
|
|
return 0;
|
|
break;
|
|
|
|
case 0x00051191: /* Acard ATP850 */
|
|
{
|
|
struct ata_pci_controller *scp =
|
|
device_get_softc(device_get_parent(ch->dev));
|
|
|
|
if (ch->unit != scp->lock)
|
|
return 0;
|
|
}
|
|
/* FALLTHROUGH */
|
|
|
|
case 0x00061191: /* Acard ATP860 */
|
|
case 0x00071191: /* Acard ATP860R */
|
|
case 0x00081191: /* Acard ATP865 */
|
|
case 0x00091191: /* Acard ATP865R */
|
|
if (ch->flags & ATA_DMA_ACTIVE) {
|
|
if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
|
|
return 0;
|
|
ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
|
|
DELAY(1);
|
|
ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
|
|
ATA_INB(ch->r_bmio, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
|
|
DELAY(1);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
if (ch->flags & ATA_DMA_ACTIVE) {
|
|
if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
|
|
return 0;
|
|
ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
|
|
DELAY(1);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
ata_pci_locknoop(struct ata_channel *ch, int type)
|
|
{
|
|
}
|
|
|
|
static void
|
|
ata_pci_serialize(struct ata_channel *ch, int flags)
|
|
{
|
|
struct ata_pci_controller *scp =
|
|
device_get_softc(device_get_parent(ch->dev));
|
|
|
|
switch (flags) {
|
|
case ATA_LF_LOCK:
|
|
if (scp->lock == ch->unit)
|
|
break;
|
|
while (!atomic_cmpset_acq_int(&scp->lock, -1, ch->unit))
|
|
tsleep((caddr_t)ch->lock_func, PRIBIO, "atalck", 1);
|
|
break;
|
|
|
|
case ATA_LF_UNLOCK:
|
|
if (scp->lock == -1 || scp->lock != ch->unit)
|
|
break;
|
|
atomic_store_rel_int(&scp->lock, -1);
|
|
wakeup((caddr_t)ch->lock_func);
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
static int
|
|
ata_pci_print_child(device_t dev, device_t child)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(child);
|
|
int retval = 0;
|
|
|
|
retval += bus_print_child_header(dev, child);
|
|
retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
|
|
|
|
if (ATA_MASTERDEV(dev))
|
|
retval += printf(" irq %d", 14 + ch->unit);
|
|
|
|
retval += bus_print_child_footer(dev, child);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static struct resource *
|
|
ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
struct ata_pci_controller *controller = device_get_softc(dev);
|
|
struct resource *res = NULL;
|
|
int unit = ((struct ata_channel *)device_get_softc(child))->unit;
|
|
int myrid;
|
|
|
|
if (type == SYS_RES_IOPORT) {
|
|
switch (*rid) {
|
|
case ATA_IOADDR_RID:
|
|
if (ATA_MASTERDEV(dev)) {
|
|
myrid = 0;
|
|
start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
|
|
end = start + ATA_IOSIZE - 1;
|
|
count = ATA_IOSIZE;
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
}
|
|
else {
|
|
myrid = 0x10 + 8 * unit;
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
}
|
|
break;
|
|
|
|
case ATA_ALTADDR_RID:
|
|
if (ATA_MASTERDEV(dev)) {
|
|
myrid = 0;
|
|
start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
|
|
end = start + ATA_ALTIOSIZE - 1;
|
|
count = ATA_ALTIOSIZE;
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
}
|
|
else {
|
|
myrid = 0x14 + 8 * unit;
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
if (res) {
|
|
start = rman_get_start(res) + 2;
|
|
end = start + ATA_ALTIOSIZE - 1;
|
|
count = ATA_ALTIOSIZE;
|
|
BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, myrid, res);
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ATA_BMADDR_RID:
|
|
if (controller->bmaddr) {
|
|
myrid = 0x20;
|
|
start = (unit == 0 ?
|
|
controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
|
|
end = start + ATA_BMIOSIZE - 1;
|
|
count = ATA_BMIOSIZE;
|
|
res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, &myrid,
|
|
start, end, count, flags);
|
|
}
|
|
}
|
|
return res;
|
|
}
|
|
|
|
if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
|
|
if (ATA_MASTERDEV(dev)) {
|
|
#ifdef __alpha__
|
|
return alpha_platform_alloc_ide_intr(unit);
|
|
#else
|
|
int irq = (unit == 0 ? 14 : 15);
|
|
|
|
return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IRQ, rid, irq, irq, 1, flags);
|
|
#endif
|
|
}
|
|
else {
|
|
/* primary and secondary channels share interrupt, keep track */
|
|
if (!controller->irq)
|
|
controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
|
|
dev, SYS_RES_IRQ,
|
|
rid, 0, ~0, 1, flags);
|
|
controller->irqcnt++;
|
|
return controller->irq;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
struct ata_pci_controller *controller = device_get_softc(dev);
|
|
int unit = ((struct ata_channel *)device_get_softc(child))->unit;
|
|
|
|
if (type == SYS_RES_IOPORT) {
|
|
switch (rid) {
|
|
case ATA_IOADDR_RID:
|
|
if (ATA_MASTERDEV(dev))
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, 0x0, r);
|
|
else
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, 0x10 + 8 * unit, r);
|
|
break;
|
|
|
|
case ATA_ALTADDR_RID:
|
|
if (ATA_MASTERDEV(dev))
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, 0x0, r);
|
|
else
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IOPORT, 0x14 + 8 * unit, r);
|
|
break;
|
|
|
|
case ATA_BMADDR_RID:
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IOPORT, 0x20, r);
|
|
default:
|
|
return ENOENT;
|
|
}
|
|
}
|
|
if (type == SYS_RES_IRQ) {
|
|
if (rid != ATA_IRQ_RID)
|
|
return ENOENT;
|
|
|
|
if (ATA_MASTERDEV(dev)) {
|
|
#ifdef __alpha__
|
|
return alpha_platform_release_ide_intr(unit, r);
|
|
#else
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
|
|
SYS_RES_IRQ, rid, r);
|
|
#endif
|
|
}
|
|
else {
|
|
/* primary and secondary channels share interrupt, keep track */
|
|
if (--controller->irqcnt)
|
|
return 0;
|
|
controller->irq = NULL;
|
|
return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
|
|
SYS_RES_IRQ, rid, r);
|
|
}
|
|
}
|
|
return EINVAL;
|
|
}
|
|
|
|
static int
|
|
ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
|
|
int flags, driver_intr_t *intr, void *arg,
|
|
void **cookiep)
|
|
{
|
|
if (ATA_MASTERDEV(dev)) {
|
|
#ifdef __alpha__
|
|
return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
|
|
#else
|
|
return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
|
|
flags, intr, arg, cookiep);
|
|
#endif
|
|
}
|
|
else
|
|
return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
|
|
flags, intr, arg, cookiep);
|
|
}
|
|
|
|
static int
|
|
ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
|
void *cookie)
|
|
{
|
|
if (ATA_MASTERDEV(dev)) {
|
|
#ifdef __alpha__
|
|
return alpha_platform_teardown_ide_intr(child, irq, cookie);
|
|
#else
|
|
return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
|
|
#endif
|
|
}
|
|
else
|
|
return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
|
|
}
|
|
|
|
static device_method_t ata_pci_methods[] = {
|
|
/* device interface */
|
|
DEVMETHOD(device_probe, ata_pci_probe),
|
|
DEVMETHOD(device_attach, ata_pci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* bus methods */
|
|
DEVMETHOD(bus_print_child, ata_pci_print_child),
|
|
DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, ata_pci_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t ata_pci_driver = {
|
|
"atapci",
|
|
ata_pci_methods,
|
|
sizeof(struct ata_pci_controller),
|
|
};
|
|
|
|
static devclass_t ata_pci_devclass;
|
|
|
|
DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
|
|
|
|
static int
|
|
ata_pcisub_probe(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
device_t *children;
|
|
int count, i;
|
|
|
|
/* find channel number on this controller */
|
|
device_get_children(device_get_parent(dev), &children, &count);
|
|
for (i = 0; i < count; i++) {
|
|
if (children[i] == dev)
|
|
ch->unit = i;
|
|
}
|
|
free(children, M_TEMP);
|
|
|
|
ch->intr_func = ata_pci_intr;
|
|
ch->chiptype = pci_get_devid(device_get_parent(dev));
|
|
switch (ch->chiptype) {
|
|
case 0x10001042: /* RZ 1000 */
|
|
case 0x10011042: /* RZ 1001 */
|
|
case 0x06401095: /* CMD 640 */
|
|
case 0x00051191: /* Acard ATP850 */
|
|
ch->lock_func = ata_pci_serialize;
|
|
break;
|
|
default:
|
|
ch->lock_func = ata_pci_locknoop;
|
|
}
|
|
return ata_probe(dev);
|
|
}
|
|
|
|
static device_method_t ata_pcisub_methods[] = {
|
|
/* device interface */
|
|
DEVMETHOD(device_probe, ata_pcisub_probe),
|
|
DEVMETHOD(device_attach, ata_attach),
|
|
DEVMETHOD(device_detach, ata_detach),
|
|
DEVMETHOD(device_resume, ata_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t ata_pcisub_driver = {
|
|
"ata",
|
|
ata_pcisub_methods,
|
|
sizeof(struct ata_channel),
|
|
};
|
|
|
|
DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
|