961 lines
18 KiB
C
961 lines
18 KiB
C
/*-
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* Copyright (c) 2006 Semihalf, Rafal Jaworowski <raj@semihalf.com>
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define KTR_BE_IO 0
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#define KTR_LE_IO 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/ktr.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <machine/md_var.h>
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#define TODO panic("%s: not implemented", __func__)
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#define MAX_EARLYBOOT_MAPPINGS 6
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static struct {
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vm_offset_t virt;
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bus_addr_t addr;
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bus_size_t size;
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int flags;
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} earlyboot_mappings[MAX_EARLYBOOT_MAPPINGS];
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static int earlyboot_map_idx = 0;
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void bs_remap_earlyboot(void);
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static __inline void *
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__ppc_ba(bus_space_handle_t bsh, bus_size_t ofs)
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{
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return ((void *)(bsh + ofs));
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}
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static int
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bs_gen_map(bus_addr_t addr, bus_size_t size, int flags,
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bus_space_handle_t *bshp)
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{
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vm_memattr_t ma;
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/*
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* Record what we did if we haven't enabled the MMU yet. We
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* will need to remap it as soon as the MMU comes up.
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*/
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if (!pmap_bootstrapped) {
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KASSERT(earlyboot_map_idx < MAX_EARLYBOOT_MAPPINGS,
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("%s: too many early boot mapping requests", __func__));
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earlyboot_mappings[earlyboot_map_idx].addr = addr;
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earlyboot_mappings[earlyboot_map_idx].virt =
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pmap_early_io_map(addr, size);
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earlyboot_mappings[earlyboot_map_idx].size = size;
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earlyboot_mappings[earlyboot_map_idx].flags = flags;
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*bshp = earlyboot_mappings[earlyboot_map_idx].virt;
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earlyboot_map_idx++;
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} else {
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ma = VM_MEMATTR_DEFAULT;
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switch (flags) {
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case BUS_SPACE_MAP_CACHEABLE:
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ma = VM_MEMATTR_CACHEABLE;
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break;
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case BUS_SPACE_MAP_PREFETCHABLE:
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ma = VM_MEMATTR_PREFETCHABLE;
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break;
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}
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*bshp = (bus_space_handle_t)pmap_mapdev_attr(addr, size, ma);
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}
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return (0);
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}
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void
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bs_remap_earlyboot(void)
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{
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int i;
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vm_offset_t pa, spa, va;
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vm_memattr_t ma;
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for (i = 0; i < earlyboot_map_idx; i++) {
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spa = earlyboot_mappings[i].addr;
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if (spa == earlyboot_mappings[i].virt &&
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pmap_dev_direct_mapped(spa, earlyboot_mappings[i].size) == 0)
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continue;
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ma = VM_MEMATTR_DEFAULT;
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switch (earlyboot_mappings[i].flags) {
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case BUS_SPACE_MAP_CACHEABLE:
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ma = VM_MEMATTR_CACHEABLE;
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break;
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case BUS_SPACE_MAP_PREFETCHABLE:
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ma = VM_MEMATTR_PREFETCHABLE;
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break;
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}
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pa = trunc_page(spa);
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va = trunc_page(earlyboot_mappings[i].virt);
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while (pa < spa + earlyboot_mappings[i].size) {
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pmap_kenter_attr(va, pa, ma);
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va += PAGE_SIZE;
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pa += PAGE_SIZE;
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}
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}
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}
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static void
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bs_gen_unmap(bus_size_t size __unused)
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{
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}
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static int
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bs_gen_subregion(bus_space_handle_t bsh, bus_size_t ofs,
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bus_size_t size __unused, bus_space_handle_t *nbshp)
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{
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*nbshp = bsh + ofs;
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return (0);
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}
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static int
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bs_gen_alloc(bus_addr_t rstart __unused, bus_addr_t rend __unused,
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bus_size_t size __unused, bus_size_t alignment __unused,
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bus_size_t boundary __unused, int flags __unused,
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bus_addr_t *bpap __unused, bus_space_handle_t *bshp __unused)
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{
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TODO;
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}
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static void
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bs_gen_free(bus_space_handle_t bsh __unused, bus_size_t size __unused)
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{
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TODO;
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}
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static void
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bs_gen_barrier(bus_space_handle_t bsh __unused, bus_size_t ofs __unused,
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bus_size_t size __unused, int flags __unused)
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{
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powerpc_iomb();
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}
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/*
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* Big-endian access functions
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*/
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static uint8_t
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bs_be_rs_1(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint8_t *addr;
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uint8_t res;
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addr = __ppc_ba(bsh, ofs);
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res = *addr;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
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return (res);
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}
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static uint16_t
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bs_be_rs_2(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint16_t *addr;
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uint16_t res;
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addr = __ppc_ba(bsh, ofs);
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res = *addr;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
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return (res);
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}
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static uint32_t
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bs_be_rs_4(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint32_t *addr;
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uint32_t res;
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addr = __ppc_ba(bsh, ofs);
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res = *addr;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
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return (res);
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}
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static uint64_t
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bs_be_rs_8(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint64_t *addr;
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uint64_t res;
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addr = __ppc_ba(bsh, ofs);
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res = *addr;
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powerpc_iomb();
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return (res);
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}
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static void
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bs_be_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
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{
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ins8(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
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{
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ins16(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
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{
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ins32(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_rm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
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{
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ins64(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
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{
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volatile uint8_t *s = __ppc_ba(bsh, ofs);
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while (cnt--)
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*addr++ = *s++;
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powerpc_iomb();
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}
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static void
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bs_be_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
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{
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volatile uint16_t *s = __ppc_ba(bsh, ofs);
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while (cnt--)
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*addr++ = *s++;
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powerpc_iomb();
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}
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static void
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bs_be_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
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{
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volatile uint32_t *s = __ppc_ba(bsh, ofs);
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while (cnt--)
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*addr++ = *s++;
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powerpc_iomb();
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}
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static void
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bs_be_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
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{
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volatile uint64_t *s = __ppc_ba(bsh, ofs);
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while (cnt--)
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*addr++ = *s++;
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powerpc_iomb();
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}
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static void
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bs_be_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val)
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{
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volatile uint8_t *addr;
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addr = __ppc_ba(bsh, ofs);
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*addr = val;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
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}
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static void
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bs_be_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val)
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{
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volatile uint16_t *addr;
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addr = __ppc_ba(bsh, ofs);
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*addr = val;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
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}
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static void
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bs_be_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val)
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{
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volatile uint32_t *addr;
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addr = __ppc_ba(bsh, ofs);
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*addr = val;
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powerpc_iomb();
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CTR4(KTR_BE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
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}
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static void
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bs_be_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val)
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{
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volatile uint64_t *addr;
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addr = __ppc_ba(bsh, ofs);
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*addr = val;
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powerpc_iomb();
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}
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static void
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bs_be_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
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bus_size_t cnt)
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{
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outsb(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
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bus_size_t cnt)
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{
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outsw(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
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bus_size_t cnt)
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{
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outsl(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
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bus_size_t cnt)
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{
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outsll(__ppc_ba(bsh, ofs), addr, cnt);
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}
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static void
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bs_be_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
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size_t cnt)
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{
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volatile uint8_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = *addr++;
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powerpc_iomb();
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}
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static void
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bs_be_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
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size_t cnt)
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{
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volatile uint16_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = *addr++;
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powerpc_iomb();
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}
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static void
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bs_be_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
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size_t cnt)
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{
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volatile uint32_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = *addr++;
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powerpc_iomb();
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}
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static void
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bs_be_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
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size_t cnt)
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{
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volatile uint64_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = *addr++;
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powerpc_iomb();
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}
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static void
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bs_be_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
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{
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volatile uint8_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d = val;
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powerpc_iomb();
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}
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static void
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bs_be_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
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{
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volatile uint16_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d = val;
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powerpc_iomb();
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}
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static void
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bs_be_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
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{
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volatile uint32_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d = val;
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powerpc_iomb();
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}
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static void
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bs_be_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
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{
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volatile uint64_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d = val;
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powerpc_iomb();
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}
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static void
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bs_be_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
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{
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volatile uint8_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = val;
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powerpc_iomb();
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}
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static void
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bs_be_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
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{
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volatile uint16_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = val;
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powerpc_iomb();
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}
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static void
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bs_be_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
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{
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volatile uint32_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = val;
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powerpc_iomb();
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}
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static void
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bs_be_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
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{
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volatile uint64_t *d = __ppc_ba(bsh, ofs);
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while (cnt--)
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*d++ = val;
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powerpc_iomb();
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}
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|
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/*
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* Little-endian access functions
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*/
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static uint8_t
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bs_le_rs_1(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint8_t *addr;
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uint8_t res;
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addr = __ppc_ba(bsh, ofs);
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res = *addr;
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powerpc_iomb();
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CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
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return (res);
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}
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static uint16_t
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bs_le_rs_2(bus_space_handle_t bsh, bus_size_t ofs)
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{
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volatile uint16_t *addr;
|
|
uint16_t res;
|
|
|
|
addr = __ppc_ba(bsh, ofs);
|
|
__asm __volatile("lhbrx %0, 0, %1" : "=r"(res) : "r"(addr));
|
|
powerpc_iomb();
|
|
CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
|
|
return (res);
|
|
}
|
|
|
|
static uint32_t
|
|
bs_le_rs_4(bus_space_handle_t bsh, bus_size_t ofs)
|
|
{
|
|
volatile uint32_t *addr;
|
|
uint32_t res;
|
|
|
|
addr = __ppc_ba(bsh, ofs);
|
|
__asm __volatile("lwbrx %0, 0, %1" : "=r"(res) : "r"(addr));
|
|
powerpc_iomb();
|
|
CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x) = %#x", __func__, bsh, ofs, res);
|
|
return (res);
|
|
}
|
|
|
|
static uint64_t
|
|
bs_le_rs_8(bus_space_handle_t bsh, bus_size_t ofs)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_rm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
|
|
{
|
|
ins8(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_rm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
|
|
{
|
|
ins16rb(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_rm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
|
|
{
|
|
ins32rb(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_rm_8(bus_space_handle_t bshh, bus_size_t ofs, uint64_t *addr, size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_rr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t *addr, size_t cnt)
|
|
{
|
|
volatile uint8_t *s = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*addr++ = *s++;
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_rr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t *addr, size_t cnt)
|
|
{
|
|
volatile uint16_t *s = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*addr++ = in16rb(s++);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_rr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t *addr, size_t cnt)
|
|
{
|
|
volatile uint32_t *s = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*addr++ = in32rb(s++);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_rr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t *addr, size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_ws_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val)
|
|
{
|
|
volatile uint8_t *addr;
|
|
|
|
addr = __ppc_ba(bsh, ofs);
|
|
*addr = val;
|
|
powerpc_iomb();
|
|
CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
|
|
}
|
|
|
|
static void
|
|
bs_le_ws_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val)
|
|
{
|
|
volatile uint16_t *addr;
|
|
|
|
addr = __ppc_ba(bsh, ofs);
|
|
__asm __volatile("sthbrx %0, 0, %1" :: "r"(val), "r"(addr));
|
|
powerpc_iomb();
|
|
CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
|
|
}
|
|
|
|
static void
|
|
bs_le_ws_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val)
|
|
{
|
|
volatile uint32_t *addr;
|
|
|
|
addr = __ppc_ba(bsh, ofs);
|
|
__asm __volatile("stwbrx %0, 0, %1" :: "r"(val), "r"(addr));
|
|
powerpc_iomb();
|
|
CTR4(KTR_LE_IO, "%s(bsh=%#x, ofs=%#x, val=%#x)", __func__, bsh, ofs, val);
|
|
}
|
|
|
|
static void
|
|
bs_le_ws_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_wm_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
|
|
bus_size_t cnt)
|
|
{
|
|
outs8(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_wm_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
|
|
bus_size_t cnt)
|
|
{
|
|
outs16rb(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_wm_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
|
|
bus_size_t cnt)
|
|
{
|
|
outs32rb(__ppc_ba(bsh, ofs), addr, cnt);
|
|
}
|
|
|
|
static void
|
|
bs_le_wm_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
|
|
bus_size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_wr_1(bus_space_handle_t bsh, bus_size_t ofs, const uint8_t *addr,
|
|
size_t cnt)
|
|
{
|
|
volatile uint8_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*d++ = *addr++;
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_wr_2(bus_space_handle_t bsh, bus_size_t ofs, const uint16_t *addr,
|
|
size_t cnt)
|
|
{
|
|
volatile uint16_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out16rb(d++, *addr++);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_wr_4(bus_space_handle_t bsh, bus_size_t ofs, const uint32_t *addr,
|
|
size_t cnt)
|
|
{
|
|
volatile uint32_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out32rb(d++, *addr++);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_wr_8(bus_space_handle_t bsh, bus_size_t ofs, const uint64_t *addr,
|
|
size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_sm_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
|
|
{
|
|
volatile uint8_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*d = val;
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sm_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
|
|
{
|
|
volatile uint16_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out16rb(d, val);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sm_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
|
|
{
|
|
volatile uint32_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out32rb(d, val);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sm_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
static void
|
|
bs_le_sr_1(bus_space_handle_t bsh, bus_size_t ofs, uint8_t val, size_t cnt)
|
|
{
|
|
volatile uint8_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
*d++ = val;
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sr_2(bus_space_handle_t bsh, bus_size_t ofs, uint16_t val, size_t cnt)
|
|
{
|
|
volatile uint16_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out16rb(d++, val);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sr_4(bus_space_handle_t bsh, bus_size_t ofs, uint32_t val, size_t cnt)
|
|
{
|
|
volatile uint32_t *d = __ppc_ba(bsh, ofs);
|
|
|
|
while (cnt--)
|
|
out32rb(d++, val);
|
|
powerpc_iomb();
|
|
}
|
|
|
|
static void
|
|
bs_le_sr_8(bus_space_handle_t bsh, bus_size_t ofs, uint64_t val, size_t cnt)
|
|
{
|
|
TODO;
|
|
}
|
|
|
|
struct bus_space bs_be_tag = {
|
|
/* mapping/unmapping */
|
|
bs_gen_map,
|
|
bs_gen_unmap,
|
|
bs_gen_subregion,
|
|
|
|
/* allocation/deallocation */
|
|
bs_gen_alloc,
|
|
bs_gen_free,
|
|
|
|
/* barrier */
|
|
bs_gen_barrier,
|
|
|
|
/* read (single) */
|
|
bs_be_rs_1,
|
|
bs_be_rs_2,
|
|
bs_be_rs_4,
|
|
bs_be_rs_8,
|
|
|
|
bs_be_rs_2,
|
|
bs_be_rs_4,
|
|
bs_be_rs_8,
|
|
|
|
/* read multiple */
|
|
bs_be_rm_1,
|
|
bs_be_rm_2,
|
|
bs_be_rm_4,
|
|
bs_be_rm_8,
|
|
|
|
bs_be_rm_2,
|
|
bs_be_rm_4,
|
|
bs_be_rm_8,
|
|
|
|
/* read region */
|
|
bs_be_rr_1,
|
|
bs_be_rr_2,
|
|
bs_be_rr_4,
|
|
bs_be_rr_8,
|
|
|
|
bs_be_rr_2,
|
|
bs_be_rr_4,
|
|
bs_be_rr_8,
|
|
|
|
/* write (single) */
|
|
bs_be_ws_1,
|
|
bs_be_ws_2,
|
|
bs_be_ws_4,
|
|
bs_be_ws_8,
|
|
|
|
bs_be_ws_2,
|
|
bs_be_ws_4,
|
|
bs_be_ws_8,
|
|
|
|
/* write multiple */
|
|
bs_be_wm_1,
|
|
bs_be_wm_2,
|
|
bs_be_wm_4,
|
|
bs_be_wm_8,
|
|
|
|
bs_be_wm_2,
|
|
bs_be_wm_4,
|
|
bs_be_wm_8,
|
|
|
|
/* write region */
|
|
bs_be_wr_1,
|
|
bs_be_wr_2,
|
|
bs_be_wr_4,
|
|
bs_be_wr_8,
|
|
|
|
bs_be_wr_2,
|
|
bs_be_wr_4,
|
|
bs_be_wr_8,
|
|
|
|
/* set multiple */
|
|
bs_be_sm_1,
|
|
bs_be_sm_2,
|
|
bs_be_sm_4,
|
|
bs_be_sm_8,
|
|
|
|
bs_be_sm_2,
|
|
bs_be_sm_4,
|
|
bs_be_sm_8,
|
|
|
|
/* set region */
|
|
bs_be_sr_1,
|
|
bs_be_sr_2,
|
|
bs_be_sr_4,
|
|
bs_be_sr_8,
|
|
|
|
bs_be_sr_2,
|
|
bs_be_sr_4,
|
|
bs_be_sr_8,
|
|
};
|
|
|
|
struct bus_space bs_le_tag = {
|
|
/* mapping/unmapping */
|
|
bs_gen_map,
|
|
bs_gen_unmap,
|
|
bs_gen_subregion,
|
|
|
|
/* allocation/deallocation */
|
|
bs_gen_alloc,
|
|
bs_gen_free,
|
|
|
|
/* barrier */
|
|
bs_gen_barrier,
|
|
|
|
/* read (single) */
|
|
bs_le_rs_1,
|
|
bs_le_rs_2,
|
|
bs_le_rs_4,
|
|
bs_le_rs_8,
|
|
|
|
bs_be_rs_2,
|
|
bs_be_rs_4,
|
|
bs_be_rs_8,
|
|
|
|
/* read multiple */
|
|
bs_le_rm_1,
|
|
bs_le_rm_2,
|
|
bs_le_rm_4,
|
|
bs_le_rm_8,
|
|
|
|
bs_be_rm_2,
|
|
bs_be_rm_4,
|
|
bs_be_rm_8,
|
|
|
|
/* read region */
|
|
bs_le_rr_1,
|
|
bs_le_rr_2,
|
|
bs_le_rr_4,
|
|
bs_le_rr_8,
|
|
|
|
bs_be_rr_2,
|
|
bs_be_rr_4,
|
|
bs_be_rr_8,
|
|
|
|
/* write (single) */
|
|
bs_le_ws_1,
|
|
bs_le_ws_2,
|
|
bs_le_ws_4,
|
|
bs_le_ws_8,
|
|
|
|
bs_be_ws_2,
|
|
bs_be_ws_4,
|
|
bs_be_ws_8,
|
|
|
|
/* write multiple */
|
|
bs_le_wm_1,
|
|
bs_le_wm_2,
|
|
bs_le_wm_4,
|
|
bs_le_wm_8,
|
|
|
|
bs_be_wm_2,
|
|
bs_be_wm_4,
|
|
bs_be_wm_8,
|
|
|
|
/* write region */
|
|
bs_le_wr_1,
|
|
bs_le_wr_2,
|
|
bs_le_wr_4,
|
|
bs_le_wr_8,
|
|
|
|
bs_be_wr_2,
|
|
bs_be_wr_4,
|
|
bs_be_wr_8,
|
|
|
|
/* set multiple */
|
|
bs_le_sm_1,
|
|
bs_le_sm_2,
|
|
bs_le_sm_4,
|
|
bs_le_sm_8,
|
|
|
|
bs_be_sm_2,
|
|
bs_be_sm_4,
|
|
bs_be_sm_8,
|
|
|
|
/* set region */
|
|
bs_le_sr_1,
|
|
bs_le_sr_2,
|
|
bs_le_sr_4,
|
|
bs_le_sr_8,
|
|
|
|
bs_be_sr_2,
|
|
bs_be_sr_4,
|
|
bs_be_sr_8,
|
|
};
|