20e8415eb4
PR 122839 is fixed in both em and in igb Second, the issue on building modules since the static kernel build changes is now resolved. I was not able to get the fancier directory hierarchy working, but this works, both em and igb build as modules now. Third, there is now support in em for two new NICs, Hartwell (or 82574) is a low cost PCIE dual port adapter that has MSIX, for this release it uses 3 vectors only, RX, TX, and LINK. In the next release I will add a second TX and RX queue. Also, there is support here for ICH10, the followon to ICH9. Both of these are early releases, general availability will follow soon. Fourth: On Hartwell and ICH10 we now have IEEE 1588 PTP support, I have implemented this in a provisional way so that early adopters may try and comment on the functionality. The IOCTL structure may change. This feature is off by default, you need to edit the Makefile and add the EM_TIMESYNC define to get the code. Enjoy all!!
128 lines
5.2 KiB
C
128 lines
5.2 KiB
C
/******************************************************************************
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Copyright (c) 2001-2008, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_ICH8LAN_H_
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#define _E1000_ICH8LAN_H_
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#define ICH_FLASH_GFPREG 0x0000
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#define ICH_FLASH_HSFSTS 0x0004
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#define ICH_FLASH_HSFCTL 0x0006
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#define ICH_FLASH_FADDR 0x0008
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#define ICH_FLASH_FDATA0 0x0010
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#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
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#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
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#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
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#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
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#define ICH_CYCLE_READ 0
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#define ICH_CYCLE_WRITE 2
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#define ICH_CYCLE_ERASE 3
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#define FLASH_GFPREG_BASE_MASK 0x1FFF
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#define FLASH_SECTOR_ADDR_SHIFT 12
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#define E1000_SHADOW_RAM_WORDS 2048
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#define ICH_FLASH_SEG_SIZE_256 256
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#define ICH_FLASH_SEG_SIZE_4K 4096
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#define ICH_FLASH_SEG_SIZE_8K 8192
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#define ICH_FLASH_SEG_SIZE_64K 65536
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#define ICH_FLASH_SECTOR_SIZE 4096
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#define ICH_FLASH_REG_MAPSIZE 0x00A0
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#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
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#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
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/* FW established a valid mode */
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#define E1000_ICH_FWSM_FW_VALID 0x00008000
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#define E1000_ICH_MNG_IAMT_MODE 0x2
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#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_DEF1_OFF2 << 8) | \
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(ID_LED_DEF1_ON2 << 4) | \
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(ID_LED_DEF1_DEF2))
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#define E1000_ICH_NVM_SIG_WORD 0x13
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#define E1000_ICH_NVM_SIG_MASK 0xC000
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#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
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#define E1000_FEXTNVM_SW_CONFIG 1
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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
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#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
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#define E1000_ICH_RAR_ENTRIES 7
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#define PHY_PAGE_SHIFT 5
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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
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((reg) & MAX_PHY_REG_ADDRESS))
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#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
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#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
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#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
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#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
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#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
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#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
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#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
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/*
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* Additional interrupts need to be handled for ICH family:
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* DSW = The FW changed the status of the DISSW bit in FWSM
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* PHYINT = The LAN connected device generates an interrupt
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* EPRST = Manageability reset event
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*/
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#define IMS_ICH_ENABLE_MASK (\
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E1000_IMS_DSW | \
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E1000_IMS_PHYINT | \
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E1000_IMS_EPRST)
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/* Additional interrupt register bit definitions */
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#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
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#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
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#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
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/* Security Processing bit Indication */
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#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
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#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
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#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
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#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
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#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
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#endif
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