223 lines
7.6 KiB
C
223 lines
7.6 KiB
C
/*-
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* Copyright (c) 1994-2000
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* Paul Richards. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* verbatim and that no modifications are made prior to this
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* point in the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name Paul Richards may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY PAUL RICHARDS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL PAUL RICHARDS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Am7990, Local Area Network Controller for Ethernet (LANCE)
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*
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* The LANCE has four Control and Status Registers(CSRs) which are accessed
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* through two bus addressable ports, the address port (RAP) and the data
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* port (RDP).
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*
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*/
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#define CSR0 0
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#define CSR1 1
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#define CSR2 2
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#define CSR3 3
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#define CSR88 88
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#define CSR89 89
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#define BCR49 49
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#define BCR32 32
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#define BCR33 33
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#define BCR34 34
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/* Control and Status Register Masks */
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/* CSR0 */
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#define ERR 0x8000
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#define BABL 0x4000
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#define CERR 0x2000
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#define MISS 0x1000
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#define MERR 0x0800
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#define RINT 0x0400
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#define TINT 0x0200
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#define IDON 0x0100
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#define INTR 0x0080
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#define INEA 0x0040
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#define RXON 0x0020
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#define TXON 0x0010
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#define TDMD 0x0008
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#define STOP 0x0004
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#define STRT 0x0002
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#define INIT 0x0001
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/*
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* CSR3
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*
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* Bits 3-15 are reserved.
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*
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*/
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#define BSWP 0x0004
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#define ACON 0x0002
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#define BCON 0x0001
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/* Initialisation block */
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struct init_block {
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u_short mode; /* Mode register */
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u_char padr[6]; /* Ethernet address */
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u_char ladrf[8]; /* Logical address filter (multicast) */
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u_short rdra; /* Low order pointer to receive ring */
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u_short rlen; /* High order pointer and no. rings */
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u_short tdra; /* Low order pointer to transmit ring */
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u_short tlen; /* High order pointer and no rings */
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};
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/* Initialisation Block Mode Register Masks */
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#define PROM 0x8000 /* Promiscuous Mode */
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#define DRCVBC 0x4000 /* Disable Receive Broadcast */
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#define DRCVPA 0x2000 /* Disable Receive Physical Address */
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#define DLNKTST 0x1000 /* Disable Link Status */
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#define DAPC 0x0800 /* Disable Automatic Polarity Correction */
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#define MENDECL 0x0400 /* MENDEC Loopback Mode */
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#define LRT 0x0200 /* Low Receive Threshold (T-MAU mode only) */
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#define TSEL 0x0200 /* Transmit Mode Select (AUI mode only) */
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#define PORTSEL 0x0180 /* Port Select bits */
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#define INTL 0x0040 /* Internal Loopback */
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#define DRTY 0x0020 /* Disable Retry */
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#define FCOLL 0x0010 /* Force Collision */
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#define DXMTFCS 0x0008 /* Disable transmit CRC (FCS) */
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#define LOOP 0x0004 /* Loopback Enabl */
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#define DTX 0x0002 /* Disable the transmitter */
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#define DRX 0x0001 /* Disable the receiver */
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/*
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* Message Descriptor Structure
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*
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* Each transmit or receive descriptor ring entry (RDRE's and TDRE's)
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* is composed of 4, 16-bit, message descriptors. They contain the following
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* information.
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*
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* 1. The address of the actual message data buffer in user (host) memory.
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* 2. The length of that message buffer.
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* 3. The status information for that particular buffer. The eight most
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* significant bits of md1 are collectively termed the STATUS of the
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* descriptor.
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*
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* Descriptor md0 contains LADR 0-15, the low order 16 bits of the 24-bit
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* address of the actual data buffer. Bits 0-7 of descriptor md1 contain
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* HADR, the high order 8-bits of the 24-bit data buffer address. Bits 8-15
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* of md1 contain the status flags of the buffer. Descriptor md2 contains the
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* buffer byte count in bits 0-11 as a two's complement number and must have
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* 1's written to bits 12-15. For the receive entry md3 has the Message Byte
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* Count in bits 0-11, this is the length of the received message and is valid
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* only when ERR is cleared and ENP is set. For the transmit entry it contains
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* more status information.
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*
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*/
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struct mds {
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u_short md0;
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u_short md1;
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short md2;
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u_short md3;
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};
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/* Receive STATUS flags for md1 */
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#define OWN 0x8000 /* Owner bit, 0=host, 1=Lance */
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#define MDERR 0x4000 /* Error */
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#define FRAM 0x2000 /* Framing error error */
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#define OFLO 0x1000 /* Silo overflow */
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#define CRC 0x0800 /* CRC error */
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#define RBUFF 0x0400 /* Buffer error */
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#define STP 0x0200 /* Start of packet */
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#define ENP 0x0100 /* End of packet */
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#define HADR 0x00FF /* High order address bits */
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/* Receive STATUS flags for md2 */
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#define BCNT 0x0FFF /* Size of data buffer as 2's comp. no. */
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/* Receive STATUS flags for md3 */
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#define MCNT 0x0FFF /* Total size of data for received packet */
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/* Transmit STATUS flags for md1 */
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#define ADD_FCS 0x2000 /* Controls generation of FCS */
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#define MORE 0x1000 /* Indicates more than one retry was needed */
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#define ONE 0x0800 /* Exactly one retry was needed */
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#define DEF 0x0400 /* Packet transmit deferred -- channel busy */
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/*
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* Transmit status flags for md2
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*
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* Same as for receive descriptor.
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*
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* BCNT 0x0FFF Size of data buffer as 2's complement number.
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*
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*/
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/* Transmit status flags for md3 */
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#define TBUFF 0x8000 /* Buffer error */
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#define UFLO 0x4000 /* Silo underflow */
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#define LCOL 0x1000 /* Late collision */
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#define LCAR 0x0800 /* Loss of carrier */
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#define RTRY 0x0400 /* Tried 16 times */
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#define TDR 0x03FF /* Time domain reflectometry */
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/* C-NET(98)S port addresses */
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#define CNET98S_RDP 0x400 /* Register Data Port */
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#define CNET98S_RAP 0x402 /* Register Address Port */
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#define CNET98S_RESET 0x404
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#define CNET98S_IDP 0x406
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#define CNET98S_EEPROM 0x40e
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/*
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* XXX - The I/O address range is fragmented in the C-NET(98)S.
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* This is the number of regs at iobase.
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*/
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#define CNET98S_IOSIZE 16 /* # of i/o addresses used. */
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/* ISA Bus Configuration Registers */
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/* XXX - Should be in ic/Am7990.h */
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#define MSRDA 0x0000 /* ISACSR0: Master Mode Read Activity */
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#define MSWRA 0x0001 /* ISACSR1: Master Mode Write Activity */
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#define MC 0x0002 /* ISACSR2: Miscellaneous Configuration */
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#define LED1 0x0005 /* ISACSR5: LED1 Status */
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#define LED2 0x0006 /* ISACSR6: LED2 Status */
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#define LED3 0x0007 /* ISACSR7: LED3 Status */
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#define LED_PSE 0x0080 /* Pulse Stretcher */
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#define LED_XMTE 0x0010 /* Transmit Status */
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#define LED_RVPOLE 0x0008 /* Receive Polarity */
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#define LED_RCVE 0x0004 /* Receive Status */
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#define LED_JABE 0x0002 /* Jabber */
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#define LED_COLE 0x0001 /* Collision */
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