6ce70ec7f9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
621 lines
19 KiB
C
621 lines
19 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu
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* Copyright (c) 1995 Paul Kranenburg
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* Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by David Miller.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_INSTR_H_
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#define _MACHINE_INSTR_H_
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/*
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* Definitions for all instruction formats
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*/
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#define IF_OP_SHIFT 30
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#define IF_OP_BITS 2
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#define IF_IMM_SHIFT 0 /* Immediate/Displacement */
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/*
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* Definitions for format 2
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*/
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#define IF_F2_RD_SHIFT 25
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#define IF_F2_RD_BITS 5
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#define IF_F2_A_SHIFT 29
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#define IF_F2_A_BITS 1
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#define IF_F2_COND_SHIFT 25
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#define IF_F2_COND_BITS 4
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#define IF_F2_RCOND_SHIFT 25
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#define IF_F2_RCOND_BITS 3
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#define IF_F2_OP2_SHIFT 22
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#define IF_F2_OP2_BITS 3
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#define IF_F2_CC1_SHIFT 21
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#define IF_F2_CC1_BITS 1
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#define IF_F2_CC0_SHIFT 20
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#define IF_F2_CC0_BITS 1
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#define IF_F2_CC_SHIFT 20 /* CC0 and CC1 combined. */
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#define IF_F2_CC_BITS 2
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#define IF_F2_D16HI_SHIFT 20
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#define IF_F2_D16HI_BITS 2
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#define IF_F2_P_SHIFT 19
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#define IF_F2_P_BITS 1
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#define IF_F2_RS1_SHIFT 14
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#define IF_F2_RS1_BITS 5
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/*
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* Definitions for format 3
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*/
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#define IF_F3_OP3_SHIFT 19
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#define IF_F3_OP3_BITS 6
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#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT
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#define IF_F3_RD_BITS IF_F2_RD_BITS
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#define IF_F3_FCN_SHIFT 25
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#define IF_F3_FCN_BITS 5
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#define IF_F3_CC1_SHIFT 26
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#define IF_F3_CC1_BITS 1
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#define IF_F3_CC0_SHIFT 25
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#define IF_F3_CC0_BITS 1
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#define IF_F3_CC_SHIFT 25 /* CC0 and CC1 combined. */
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#define IF_F3_CC_BITS 2
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#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT
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#define IF_F3_RS1_BITS IF_F2_RS1_BITS
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#define IF_F3_I_SHIFT 13
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#define IF_F3_I_BITS 1
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#define IF_F3_X_SHIFT 12
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#define IF_F3_X_BITS 1
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#define IF_F3_RCOND_SHIFT 10
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#define IF_F3_RCOND_BITS 3
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#define IF_F3_IMM_ASI_SHIFT 5
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#define IF_F3_IMM_ASI_BITS 8
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#define IF_F3_OPF_SHIFT 5
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#define IF_F3_OPF_BITS 9
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#define IF_F3_CMASK_SHIFT 4
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#define IF_F3_CMASK_BITS 3
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#define IF_F3_RS2_SHIFT 0
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#define IF_F3_RS2_BITS 5
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#define IF_F3_SHCNT32_SHIFT 0
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#define IF_F3_SHCNT32_BITS 5
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#define IF_F3_SHCNT64_SHIFT 0
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#define IF_F3_SHCNT64_BITS 6
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/*
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* Definitions for format 4
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*/
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#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT
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#define IF_F4_OP3_BITS IF_F3_OP3_BITS
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#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT
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#define IF_F4_RD_BITS IF_F2_RD_BITS
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#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT
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#define IF_F4_RS1_BITS IF_F2_RS1_BITS
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#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */
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#define IF_F4_TCOND_BITS IF_F2_COND_BITS
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#define IF_F4_CC2_SHIFT 18
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#define IF_F4_CC2_BITS 1
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#define IF_F4_COND_SHIFT 14
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#define IF_F4_COND_BITS 4
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#define IF_F4_I_SHIFT IF_F3_I_SHIFT
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#define IF_F4_I_BITS IF_F3_I_BITS
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#define IF_F4_OPF_CC_SHIFT 11
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#define IF_F4_OPF_CC_BITS 3
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#define IF_F4_CC1_SHIFT 12
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#define IF_F4_CC1_BITS 1
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#define IF_F4_CC0_SHIFT 11
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#define IF_F4_CC0_BITS 1
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#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT
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#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS
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#define IF_F4_OPF_LOW_SHIFT 5
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#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT
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#define IF_F4_RS2_BITS IF_F3_RS2_BITS
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#define IF_F4_SW_TRAP_SHIFT 0
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#define IF_F4_SW_TRAP_BITS 7
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/*
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* Macros to decode instructions
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*/
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/* Extract a field */
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#define IF_MASK(s, w) (((1 << (w)) - 1) << (s))
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#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s))
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#define IF_DECODE(x, f) \
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IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
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/* Sign-extend a field of width W */
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#define IF_SEXT(x, w) \
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(((x) & (1L << ((w) - 1))) != 0 ? \
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(-1L - ((x) ^ ((1L << (w)) - 1))) : (x))
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#if 0
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/*
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* The following C variant is from db_disassemble.c, and surely faster, but it
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* relies on behaviour that is undefined by the C standard (>> in conjunction
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* with signed negative arguments).
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*/
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#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w))
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/* Assembler version of the above */
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#define IF_SEXT(v, w) \
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{ u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" :
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"=r" (t) : "r" (v) : "i" (64 - w)); t)}
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#endif
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/* All instruction formats */
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#define IF_OP(i) IF_DECODE(i, OP)
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/* Instruction format 2 */
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#define IF_F2_RD(i) IF_DECODE((i), F2_RD)
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#define IF_F2_A(i) IF_DECODE((i), F2_A)
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#define IF_F2_COND(i) IF_DECODE((i), F2_COND)
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#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND)
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#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2)
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#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1)
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#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0)
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#define IF_F2_CC(i) IF_DECODE((i), F2_CC)
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#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI)
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#define IF_F2_P(i) IF_DECODE((i), F2_P)
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#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1)
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/* Instruction format 3 */
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#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3)
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#define IF_F3_RD(i) IF_F2_RD((i))
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#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN)
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#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1)
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#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0)
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#define IF_F3_CC(i) IF_DECODE((i), F3_CC)
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#define IF_F3_RS1(i) IF_F2_RS1((i))
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#define IF_F3_I(i) IF_DECODE((i), F3_I)
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#define IF_F3_X(i) IF_DECODE((i), F3_X)
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#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND)
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#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI)
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#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF)
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#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK)
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#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2)
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#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32)
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#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64)
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/* Instruction format 4 */
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#define IF_F4_OP3(i) IF_F3_OP3((i))
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#define IF_F4_RD(i) IF_F3_RD((i))
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#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND)
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#define IF_F4_RS1(i) IF_F3_RS1((i))
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#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2)
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#define IF_F4_COND(i) IF_DECODE((i), F4_COND)
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#define IF_F4_I(i) IF_F3_I((i))
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#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC)
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#define IF_F4_RCOND(i) IF_F3_RCOND((i))
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#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w))
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#define IF_F4_RS2(i) IF_F3_RS2((i))
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#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP)
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/* Extract an immediate from an instruction, with an without sign extension */
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#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w))
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#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); })
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/*
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* Macros to encode instructions
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*/
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#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s))
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#define IF_ENCODE(x, f) \
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IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS)
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/* All instruction formats */
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#define EIF_OP(x) IF_ENCODE((x), OP)
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/* Instruction format 2 */
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#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD)
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#define EIF_F2_A(x) IF_ENCODE((x), F2_A)
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#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND)
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#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND)
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#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2)
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#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1)
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#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0)
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#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI)
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#define EIF_F2_P(x) IF_ENCODE((x), F2_P)
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#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1)
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/* Instruction format 3 */
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#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3)
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#define EIF_F3_RD(x) EIF_F2_RD((x))
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#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN)
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#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1)
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#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0)
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#define EIF_F3_RS1(x) EIF_F2_RS1((x))
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#define EIF_F3_I(x) IF_ENCODE((x), F3_I)
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#define EIF_F3_X(x) IF_ENCODE((x), F3_X)
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#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND)
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#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI)
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#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF)
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#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK)
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#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2)
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#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32)
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#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64)
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/* Instruction format 4 */
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#define EIF_F4_OP3(x) EIF_F3_OP3((x))
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#define EIF_F4_RD(x) EIF_F2_RD((x))
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#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND)
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#define EIF_F4_RS1(x) EIF_F2_RS1((x))
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#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2)
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#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND)
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#define EIF_F4_I(x) EIF_F3_I((x))
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#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC)
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#define EIF_F4_RCOND(x) EIF_F3_RCOND((x))
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#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w))
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#define EIF_F4_RS2(x) EIF_F3_RS2((x))
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#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP)
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/* Immediates */
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#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w))
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#define EIF_SIMM(x, w) IF_EIMM((x), (w))
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/*
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* OP field values (specifying the instruction format)
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*/
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#define IOP_FORM2 0x00 /* Format 2: sethi, branches */
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#define IOP_CALL 0x01 /* Format 1: call */
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#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */
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#define IOP_LDST 0x03 /* Format 4: loads and stores */
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/*
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* OP2/OP3 values (specifying the actual instruction)
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*/
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/* OP2 values for format 2 (OP = 0) */
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#define INS0_ILLTRAP 0x00
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#define INS0_BPcc 0x01
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#define INS0_Bicc 0x02
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#define INS0_BPr 0x03
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#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */
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#define INS0_FBPfcc 0x05
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#define INS0_FBfcc 0x06
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/* undefined 0x07 */
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/* OP3 values for Format 3 and 4 (OP = 2) */
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#define INS2_ADD 0x00
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#define INS2_AND 0x01
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#define INS2_OR 0x02
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#define INS2_XOR 0x03
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#define INS2_SUB 0x04
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#define INS2_ANDN 0x05
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#define INS2_ORN 0x06
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#define INS2_XNOR 0x07
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#define INS2_ADDC 0x08
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#define INS2_MULX 0x09
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#define INS2_UMUL 0x0a
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#define INS2_SMUL 0x0b
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#define INS2_SUBC 0x0c
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#define INS2_UDIVX 0x0d
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#define INS2_UDIV 0x0e
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#define INS2_SDIV 0x0f
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#define INS2_ADDcc 0x10
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#define INS2_ANDcc 0x11
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#define INS2_ORcc 0x12
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#define INS2_XORcc 0x13
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#define INS2_SUBcc 0x14
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#define INS2_ANDNcc 0x15
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#define INS2_ORNcc 0x16
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#define INS2_XNORcc 0x17
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#define INS2_ADDCcc 0x18
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/* undefined 0x19 */
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#define INS2_UMULcc 0x1a
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#define INS2_SMULcc 0x1b
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#define INS2_SUBCcc 0x1c
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/* undefined 0x1d */
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#define INS2_UDIVcc 0x1e
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#define INS2_SDIVcc 0x1f
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#define INS2_TADDcc 0x20
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#define INS2_TSUBcc 0x21
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#define INS2_TADDccTV 0x22
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#define INS2_TSUBccTV 0x23
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#define INS2_MULScc 0x24
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#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */
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#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */
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#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */
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#define INS2_RD 0x28 /* and MEMBAR, STBAR */
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/* undefined 0x29 */
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#define INS2_RDPR 0x2a
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#define INS2_FLUSHW 0x2b
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#define INS2_MOVcc 0x2c
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#define INS2_SDIVX 0x2d
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#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */
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#define INS2_MOVr 0x2f
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#define INS2_WR 0x30 /* and SIR */
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#define INS2_SV_RSTR 0x31 /* saved, restored */
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#define INS2_WRPR 0x32
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/* undefined 0x33 */
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#define INS2_FPop1 0x34 /* further encoded in opf field */
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#define INS2_FPop2 0x35 /* further encoded in opf field */
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#define INS2_IMPLDEP1 0x36
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#define INS2_IMPLDEP2 0x37
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#define INS2_JMPL 0x38
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#define INS2_RETURN 0x39
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#define INS2_Tcc 0x3a
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#define INS2_FLUSH 0x3b
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#define INS2_SAVE 0x3c
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#define INS2_RESTORE 0x3d
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#define INS2_DONE_RETR 0x3e /* done, retry */
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/* undefined 0x3f */
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/* OP3 values for format 3 (OP = 3) */
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#define INS3_LDUW 0x00
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#define INS3_LDUB 0x01
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#define INS3_LDUH 0x02
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#define INS3_LDD 0x03
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#define INS3_STW 0x04
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#define INS3_STB 0x05
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#define INS3_STH 0x06
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#define INS3_STD 0x07
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#define INS3_LDSW 0x08
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#define INS3_LDSB 0x09
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#define INS3_LDSH 0x0a
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#define INS3_LDX 0x0b
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/* undefined 0x0c */
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#define INS3_LDSTUB 0x0d
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#define INS3_STX 0x0e
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#define INS3_SWAP 0x0f
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#define INS3_LDUWA 0x10
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#define INS3_LDUBA 0x11
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#define INS3_LDUHA 0x12
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#define INS3_LDDA 0x13
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#define INS3_STWA 0x14
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#define INS3_STBA 0x15
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#define INS3_STHA 0x16
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#define INS3_STDA 0x17
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#define INS3_LDSWA 0x18
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#define INS3_LDSBA 0x19
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#define INS3_LDSHA 0x1a
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#define INS3_LDXA 0x1b
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/* undefined 0x1c */
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#define INS3_LDSTUBA 0x1d
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#define INS3_STXA 0x1e
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#define INS3_SWAPA 0x1f
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#define INS3_LDF 0x20
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#define INS3_LDFSR 0x21 /* and LDXFSR */
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#define INS3_LDQF 0x22
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#define INS3_LDDF 0x23
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#define INS3_STF 0x24
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#define INS3_STFSR 0x25 /* and STXFSR */
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#define INS3_STQF 0x26
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#define INS3_STDF 0x27
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/* undefined 0x28 - 0x2c */
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#define INS3_PREFETCH 0x2d
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/* undefined 0x2e - 0x2f */
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#define INS3_LDFA 0x30
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/* undefined 0x31 */
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#define INS3_LDQFA 0x32
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#define INS3_LDDFA 0x33
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#define INS3_STFA 0x34
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/* undefined 0x35 */
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#define INS3_STQFA 0x36
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#define INS3_STDFA 0x37
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/* undefined 0x38 - 0x3b */
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#define INS3_CASA 0x39
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#define INS3_PREFETCHA 0x3a
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#define INS3_CASXA 0x3b
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/*
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* OPF values (floating point instructions, IMPLDEP)
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*/
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/*
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* These values are or'ed to the FPop values to get the instructions.
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* They describe the operand type(s).
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*/
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#define INSFP_i 0x000 /* 32-bit int */
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#define INSFP_s 0x001 /* 32-bit single */
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#define INSFP_d 0x002 /* 64-bit double */
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#define INSFP_q 0x003 /* 128-bit quad */
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/* FPop1. The comments give the types for which this instruction is defined. */
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#define INSFP1_FMOV 0x000 /* s, d, q */
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#define INSFP1_FNEG 0x004 /* s, d, q */
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#define INSFP1_FABS 0x008 /* s, d, q */
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#define INSFP1_FSQRT 0x028 /* s, d, q */
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#define INSFP1_FADD 0x040 /* s, d, q */
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#define INSFP1_FSUB 0x044 /* s, d, q */
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#define INSFP1_FMUL 0x048 /* s, d, q */
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#define INSFP1_FDIV 0x04c /* s, d, q */
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#define INSFP1_FsMULd 0x068 /* s */
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#define INSFP1_FdMULq 0x06c /* d */
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#define INSFP1_FTOx 0x080 /* s, d, q */
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#define INSFP1_FxTOs 0x084 /* special: i only */
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#define INSFP1_FxTOd 0x088 /* special: i only */
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#define INSFP1_FxTOq 0x08c /* special: i only */
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#define INSFP1_FTOs 0x0c4 /* i, d, q */
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#define INSFP1_FTOd 0x0c8 /* i, s, q */
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#define INSFP1_FTOq 0x0cc /* i, s, d */
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#define INSFP1_FTOi 0x0d0 /* i, s, d */
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/* FPop2 */
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#define INSFP2_FMOV_CCMUL 0x40
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#define INSFP2_FMOV_CCOFFS 0x00
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/* Use the IFCC_* constants for cc. Operand types: s, d, q */
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#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS)
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#define INSFP2_FMOV_RCMUL 0x20
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#define INSFP2_FMOV_RCOFFS 0x04
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/* Use the IRCOND_* constants for rc. Operand types: s, d, q */
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#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS)
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#define INSFP2_FCMP 0x050 /* s, d, q */
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#define INSFP2_FCMPE 0x054 /* s, d, q */
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/* Decode 5-bit register field into 6-bit number (for doubles and quads). */
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#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5))
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/* IMPLDEP1 for Sun UltraSparc */
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#define IIDP1_EDGE8 0x00
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#define IIDP1_EDGE8N 0x01 /* US-III */
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#define IIDP1_EDGE8L 0x02
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#define IIDP1_EDGE8LN 0x03 /* US-III */
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#define IIDP1_EDGE16 0x04
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#define IIDP1_EDGE16N 0x05 /* US-III */
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#define IIDP1_EDGE16L 0x06
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#define IIDP1_EDGE16LN 0x07 /* US-III */
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#define IIDP1_EDGE32 0x08
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#define IIDP1_EDGE32N 0x09 /* US-III */
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#define IIDP1_EDGE32L 0x0a
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#define IIDP1_EDGE32LN 0x0b /* US-III */
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#define IIDP1_ARRAY8 0x10
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#define IIDP1_ARRAY16 0x12
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#define IIDP1_ARRAY32 0x14
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#define IIDP1_ALIGNADDRESS 0x18
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#define IIDP1_BMASK 0x19 /* US-III */
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#define IIDP1_ALIGNADDRESS_L 0x1a
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#define IIDP1_FCMPLE16 0x20
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#define IIDP1_FCMPNE16 0x22
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#define IIDP1_FCMPLE32 0x24
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#define IIDP1_FCMPNE32 0x26
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#define IIDP1_FCMPGT16 0x28
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#define IIDP1_FCMPEQ16 0x2a
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#define IIDP1_FCMPGT32 0x2c
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#define IIDP1_FCMPEQ32 0x2e
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#define IIDP1_FMUL8x16 0x31
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#define IIDP1_FMUL8x16AU 0x33
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#define IIDP1_FMUL8X16AL 0x35
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#define IIDP1_FMUL8SUx16 0x36
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#define IIDP1_FMUL8ULx16 0x37
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#define IIDP1_FMULD8SUx16 0x38
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#define IIDP1_FMULD8ULx16 0x39
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#define IIDP1_FPACK32 0x3a
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#define IIDP1_FPACK16 0x3b
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#define IIDP1_FPACKFIX 0x3d
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#define IIDP1_PDIST 0x3e
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#define IIDP1_FALIGNDATA 0x48
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#define IIDP1_FPMERGE 0x4b
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#define IIDP1_BSHUFFLE 0x4c /* US-III */
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#define IIDP1_FEXPAND 0x4d
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#define IIDP1_FPADD16 0x50
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#define IIDP1_FPADD16S 0x51
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#define IIDP1_FPADD32 0x52
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#define IIDP1_FPADD32S 0x53
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#define IIDP1_SUB16 0x54
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#define IIDP1_SUB16S 0x55
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#define IIDP1_SUB32 0x56
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#define IIDP1_SUB32S 0x57
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#define IIDP1_FZERO 0x60
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#define IIDP1_FZEROS 0x61
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#define IIDP1_FNOR 0x62
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#define IIDP1_FNORS 0x63
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#define IIDP1_FANDNOT2 0x64
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#define IIDP1_FANDNOT2S 0x65
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#define IIDP1_NOT2 0x66
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#define IIDP1_NOT2S 0x67
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#define IIDP1_FANDNOT1 0x68
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#define IIDP1_FANDNOT1S 0x69
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#define IIDP1_FNOT1 0x6a
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#define IIDP1_FNOT1S 0x6b
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#define IIDP1_FXOR 0x6c
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#define IIDP1_FXORS 0x6d
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#define IIDP1_FNAND 0x6e
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#define IIDP1_FNANDS 0x6f
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#define IIDP1_FAND 0x70
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#define IIDP1_FANDS 0x71
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#define IIDP1_FXNOR 0x72
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#define IIDP1_FXNORS 0x73
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#define IIDP1_FSRC1 0x74
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#define IIDP1_FSRC1S 0x75
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#define IIDP1_FORNOT2 0x76
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#define IIDP1_FORNOT2S 0x77
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#define IIDP1_FSRC2 0x78
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#define IIDP1_FSRC2S 0x79
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#define IIDP1_FORNOT1 0x7a
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#define IIDP1_FORNOT1S 0x7b
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#define IIDP1_FOR 0x7c
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#define IIDP1_FORS 0x7d
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#define IIDP1_FONE 0x7e
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#define IIDP1_FONES 0x7f
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#define IIDP1_SHUTDOWN 0x80
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#define IIDP1_SIAM 0x81 /* US-III */
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/*
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* Instruction modifiers
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*/
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/* cond values for integer ccr's */
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#define IICOND_N 0x00
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#define IICOND_E 0x01
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#define IICOND_LE 0x02
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#define IICOND_L 0x03
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#define IICOND_LEU 0x04
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#define IICOND_CS 0x05
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#define IICOND_NEG 0x06
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#define IICOND_VS 0x07
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#define IICOND_A 0x08
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#define IICOND_NE 0x09
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#define IICOND_G 0x0a
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#define IICOND_GE 0x0b
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#define IICOND_GU 0x0c
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#define IICOND_CC 0x0d
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#define IICOND_POS 0x0e
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#define IICOND_VC 0x0f
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/* cond values for fp ccr's */
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#define IFCOND_N 0x00
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#define IFCOND_NE 0x01
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#define IFCOND_LG 0x02
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#define IFCOND_UL 0x03
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#define IFCOND_L 0x04
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#define IFCOND_UG 0x05
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#define IFCOND_G 0x06
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#define IFCOND_U 0x07
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#define IFCOND_A 0x08
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#define IFCOND_E 0x09
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#define IFCOND_UE 0x0a
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#define IFCOND_GE 0x0b
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#define IFCOND_UGE 0x0c
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#define IFCOND_LE 0x0d
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#define IFCOND_ULE 0x0e
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#define IFCOND_O 0x0f
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/* rcond values for BPr, MOVr, FMOVr */
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#define IRCOND_Z 0x01
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#define IRCOND_LEZ 0x02
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#define IRCOND_LZ 0x03
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#define IRCOND_NZ 0x05
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#define IRCOND_GZ 0x06
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#define IRCOND_GEZ 0x07
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/* cc values for MOVcc and FMOVcc */
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#define IFCC_ICC 0x04
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#define IFCC_XCC 0x06
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/* if true, the lower 2 bits are the fcc number */
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#define IFCC_FCC(c) ((c) & 3)
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#define IFCC_GET_FCC(c) ((c) & 3)
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#define IFCC_ISFCC(c) (((c) & 4) == 0)
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/* cc values for BPc and Tcc */
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#define IBCC_ICC 0x00
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#define IBCC_XCC 0x02
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/*
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* Integer registers
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*/
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#define IREG_G0 0x00
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#define IREG_O0 0x08
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#define IREG_L0 0x10
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#define IREQ_I0 0x18
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#endif /* !_MACHINE_INSTR_H_ */
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