33f1cb93f9
specific instructions such as rpcc and mb. This should provide some performance improvements and will allow me to delete the file pal.s. To allow people time to update their loadable modules, I will leave pal.s alone for now.
565 lines
14 KiB
C
565 lines
14 KiB
C
/* $FreeBSD$ */
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/* From: NetBSD: alpha_cpu.h,v 1.15 1997/09/20 19:02:34 mjacob Exp */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#ifndef __ALPHA_ALPHA_CPU_H__
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#define __ALPHA_ALPHA_CPU_H__
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/*
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* Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
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*
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* Definitions for:
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*
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* Process Control Block
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* Interrupt/Exception/Syscall Stack Frame
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* Processor Status Register
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* Machine Check Error Summary Register
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* Machine Check Logout Area
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* Virtual Memory Management
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* Kernel Entry Vectors
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* MMCSR Fault Type Codes
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* Translation Buffer Invalidation
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*
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* and miscellaneous PALcode operations.
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*/
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/*
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* Process Control Block definitions [OSF/1 PALcode Specific]
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*/
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struct alpha_pcb {
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unsigned long apcb_ksp; /* kernel stack ptr */
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unsigned long apcb_usp; /* user stack ptr */
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unsigned long apcb_ptbr; /* page table base reg */
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unsigned int apcb_cpc; /* charged process cycles */
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unsigned int apcb_asn; /* address space number */
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unsigned long apcb_unique; /* process unique value */
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unsigned long apcb_flags; /* flags; see below */
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unsigned long apcb_decrsv0; /* DEC reserved */
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unsigned long apcb_decrsv1; /* DEC reserved */
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};
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#define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
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#define ALPHA_PCB_FLAGS_PME 0x4000000000000000
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/*
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* Interrupt/Exception/Syscall "Hardware" (really PALcode)
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* Stack Frame definitions
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*
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* These are quadword offsets from the sp on kernel entry, i.e.
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* to get to the value in question you access (sp + (offset * 8)).
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*
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* On syscall entry, A0-A2 aren't written to memory but space
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* _is_ reserved for them.
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*/
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#define ALPHA_HWFRAME_PS 0 /* processor status register */
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#define ALPHA_HWFRAME_PC 1 /* program counter */
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#define ALPHA_HWFRAME_GP 2 /* global pointer */
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#define ALPHA_HWFRAME_A0 3 /* a0 */
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#define ALPHA_HWFRAME_A1 4 /* a1 */
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#define ALPHA_HWFRAME_A2 5 /* a2 */
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#define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */
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/*
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* Processor Status Register [OSF/1 PALcode Specific]
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*
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* Includes user/kernel mode bit, interrupt priority levels, etc.
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*/
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#define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
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#define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
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#define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
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#define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
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#define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
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#define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
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#define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
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#define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
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/* Convenience constants: what must be set/clear in user mode */
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#define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
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#define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
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/*
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* Interrupt Type Code Definitions [OSF/1 PALcode Specific]
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*/
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#define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */
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#define ALPHA_INTR_CLOCK 1 /* clock interrupt */
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#define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */
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#define ALPHA_INTR_DEVICE 3 /* device interrupt */
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#define ALPHA_INTR_PERF 4 /* performance counter */
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#define ALPHA_INTR_PASSIVE 5 /* passive release */
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/*
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* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
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*
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* The following bits are values as read. On write, _PCE, _SCE, and
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* _MIP are "write 1 to clear."
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*/
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#define ALPHA_MCES_IMP \
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0xffffffff00000000 /* impl. dependent */
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#define ALPHA_MCES_RSVD \
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0x00000000ffffffe0 /* reserved */
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#define ALPHA_MCES_DSC \
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0x0000000000000010 /* disable system correctable error reporting */
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#define ALPHA_MCES_DPC \
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0x0000000000000008 /* disable processor correctable error reporting */
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#define ALPHA_MCES_PCE \
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0x0000000000000004 /* processor correctable error in progress */
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#define ALPHA_MCES_SCE \
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0x0000000000000002 /* system correctable error in progress */
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#define ALPHA_MCES_MIP \
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0x0000000000000001 /* machine check in progress */
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/*
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* Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
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*/
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struct alpha_logout_area {
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unsigned int la_frame_size; /* frame size */
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unsigned int la_flags; /* flags; see below */
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unsigned int la_cpu_offset; /* offset to cpu area */
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unsigned int la_system_offset; /* offset to system area */
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};
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#define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */
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#define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */
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#define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */
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#define ALPHA_LOGOUT_NOT_BUILT \
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(struct alpha_logout_area *)0xffffffffffffffff)
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#define ALPHA_LOGOUT_PAL_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + 16)
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#define ALPHA_LOGOUT_PAL_SIZE(lap) \
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((lap)->la_cpu_offset - 16)
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#define ALPHA_LOGOUT_CPU_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
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#define ALPHA_LOGOUT_CPU_SIZE(lap) \
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((lap)->la_system_offset - (lap)->la_cpu_offset)
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#define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
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(unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
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#define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
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((lap)->la_frame_size - (lap)->la_system_offset)
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/*
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* Virtual Memory Management definitions [OSF/1 PALcode Specific]
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*
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* Includes user and kernel space addresses and information,
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* page table entry definitions, etc.
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*
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* NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
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*/
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#define ALPHA_PGSHIFT 13 /* bits that index within page */
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#define ALPHA_PTSHIFT 10 /* bits that index within page tables */
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#define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
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#define ALPHA_L3SHIFT ALPHA_PGSHIFT
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#define ALPHA_L2SHIFT (ALPHA_L3SHIFT+ALPHA_PTSHIFT)
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#define ALPHA_L1SHIFT (ALPHA_L2SHIFT+ALPHA_PTSHIFT)
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#define ALPHA_USEG_BASE 0 /* virtual */
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#define ALPHA_USEG_END 0x000003ffffffffffLL
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#define ALPHA_K0SEG_BASE 0xfffffc0000000000LL /* direct-mapped */
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#define ALPHA_K0SEG_END 0xfffffdffffffffffLL
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#define ALPHA_K1SEG_BASE 0xfffffe0000000000LL /* virtual */
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#define ALPHA_K1SEG_END 0xffffffffffffffffLL
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#define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
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#define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
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#define ALPHA_PTE_VALID 0x0001
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#define ALPHA_PTE_FAULT_ON_READ 0x0002
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#define ALPHA_PTE_FAULT_ON_WRITE 0x0004
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#define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008
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#define ALPHA_PTE_ASM 0x0010 /* addr. space match */
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#define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */
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#define ALPHA_PTE_PROT 0xff00
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#define ALPHA_PTE_KR 0x0100
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#define ALPHA_PTE_UR 0x0200
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#define ALPHA_PTE_KW 0x1000
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#define ALPHA_PTE_UW 0x2000
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#define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
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#define ALPHA_PTE_SOFTWARE 0xffff0000
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#define ALPHA_PTE_PFN 0xffffffff00000000
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#define ALPHA_PTE_TO_PFN(pte) ((u_long)(pte) >> 32)
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#define ALPHA_PTE_FROM_PFN(pfn) ((u_long)(pfn) << 32)
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typedef unsigned long alpha_pt_entry_t;
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/*
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* Kernel Entry Vectors. [OSF/1 PALcode Specific]
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*/
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#define ALPHA_KENTRY_INT 0
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#define ALPHA_KENTRY_ARITH 1
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#define ALPHA_KENTRY_MM 2
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#define ALPHA_KENTRY_IF 3
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#define ALPHA_KENTRY_UNA 4
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#define ALPHA_KENTRY_SYS 5
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/*
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* MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
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*/
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#define ALPHA_MMCSR_INVALTRANS 0
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#define ALPHA_MMCSR_ACCESS 1
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#define ALPHA_MMCSR_FOR 2
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#define ALPHA_MMCSR_FOE 3
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#define ALPHA_MMCSR_FOW 4
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/*
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* Instruction Fault Type Codes. [OSF/1 PALcode Specific]
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*/
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#define ALPHA_IF_CODE_BPT 0
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#define ALPHA_IF_CODE_BUGCHK 1
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#define ALPHA_IF_CODE_GENTRAP 2
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#define ALPHA_IF_CODE_FEN 3
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#define ALPHA_IF_CODE_OPDEC 4
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/*
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* Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
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*/
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#define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */
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#define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */
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#define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */
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#define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */
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#define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */
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/*
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* Bits used in the amask instruction [EV56 and later]
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*/
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#define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */
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#define ALPHA_AMASK_FIX 0x0002 /* sqrt and f <-> i conversion extension */
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#define ALPHA_AMASK_CIX 0x0004 /* count extension */
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#define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */
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#define ALPHA_AMASK_PRECISE 0x0200 /* Precise arithmetic traps */
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/*
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* Chip family IDs returned by implver instruction
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*/
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#define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */
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#define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */
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#define ALPHA_IMPLVER_EV6 2 /* EV6 */
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/*
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* Inlines for Alpha instructions normally inaccessible from C.
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*/
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static __inline u_int64_t
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alpha_amask(u_int64_t mask)
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{
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u_int64_t result;
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__asm__ __volatile__ (
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"amask %1,%0"
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: "=r" (result)
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: "r" (mask));
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return result;
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}
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static __inline unsigned long
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alpha_implver(void)
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{
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u_int64_t result;
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__asm__ __volatile__ (
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"implver %0"
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: "=r" (result));
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return result;
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}
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static __inline unsigned long
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alpha_rpcc(void)
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{
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u_int64_t result;
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__asm__ __volatile__ (
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"rpcc %0"
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: "=r" (result));
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return result;
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}
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static __inline void
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alpha_mb(void)
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{
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__asm__ __volatile__ ("mb");
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}
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static __inline void
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alpha_wmb(void)
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{
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/*
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* XXX dfr: NetBSD originally had mb instead of wmb for
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* alpha_wmb(). I'm not sure why so I'm leaving it alone. I
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* think it should be safe to use wmb though.
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*/
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__asm__ __volatile__ ("mb");
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}
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/*
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* Inlines for OSF/1 PALcode operations.
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*/
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static __inline void
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alpha_pal_halt(void)
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{
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__asm__ __volatile__ ("call_pal 0x0 #PAL_halt");
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}
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static __inline void
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alpha_pal_cflush(u_int64_t pfn)
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{
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register u_int64_t a0 __asm__("$16") = pfn;
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__asm__ __volatile__ (
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"call_pal 0x1 #PAL_cflush"
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:
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: "r" (a0));
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}
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static __inline void
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alpha_pal_draina(void)
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{
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__asm__ __volatile__ ("call_pal 0x2 #PAL_draina" : : : "memory");
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}
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static __inline void
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alpha_pal_wripir(u_int64_t ipir)
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{
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register u_int64_t a0 __asm__("$16") = ipir;
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__asm__ __volatile__ (
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"call_pal 0xd #PAL_ipir"
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: "=r" (a0)
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: "0" (a0)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline u_int64_t
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alpha_pal_rdmces(void)
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{
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register u_int64_t v0 __asm__("$0");
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__asm__ __volatile__ (
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"call_pal 0x10 #PAL_OSF1_rdmces"
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: "=r" (v0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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return v0;
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}
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static __inline void
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alpha_pal_wrmces(u_int64_t mces)
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{
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register u_int64_t a0 __asm__("$16") = mces;
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__asm__ __volatile__ (
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"call_pal 0x11 #PAL_wrmces"
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: "=r" (a0)
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: "0" (a0)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline void
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alpha_pal_wrfen(u_int64_t fen)
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{
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register u_int64_t a0 __asm__("$16") = fen;
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__asm__ __volatile__ (
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"call_pal 0x2b #PAL_wrfen"
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: "=r" (a0)
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: "0" (a0)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline void
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alpha_pal_wrvptptr(u_int64_t vptptr)
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{
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register u_int64_t a0 __asm__("$16") = vptptr;
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__asm__ __volatile__ (
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"call_pal 0x2d #PAL_wrvptptr"
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: "=r" (a0)
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: "0" (a0)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline u_int64_t
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alpha_pal_swpctx(u_int64_t pcb)
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{
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register u_int64_t a0 __asm__("$16") = pcb;
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register u_int64_t v0 __asm__("$0");
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__asm__ __volatile__ (
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"call_pal 0x30 #PAL_OSF1_swpctx"
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: "=r" (v0), "=r" (a0)
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: "1" (a0)
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: "$1", "$22", "$23", "$24", "$25", "memory");
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return v0;
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}
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static __inline void
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alpha_pal_wrval(u_int64_t sysvalue)
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{
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register u_int64_t a0 __asm__("$16") = sysvalue;
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__asm__ __volatile__ (
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"call_pal 0x31 #PAL_wrval"
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: "=r" (a0)
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: "0" (a0)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline u_int64_t
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alpha_pal_rdval(void)
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{
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register u_int64_t v0 __asm__("$0");
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__asm__ __volatile__ (
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"call_pal 0x32 #PAL_OSF1_rdval"
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: "=r" (v0)
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:
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: "$1", "$22", "$23", "$24", "$25");
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return v0;
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}
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static __inline void
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alpha_pal_tbi(u_int64_t op, u_int64_t va)
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{
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register u_int64_t a0 __asm__("$16") = op;
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register u_int64_t a1 __asm__("$17") = va;
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__asm__ __volatile__ (
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"call_pal 0x33 #PAL_OSF1_tbi"
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: "=r" (a0), "=r" (a1)
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: "0" (a0), "1" (a1)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline void
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alpha_pal_wrent(void *ent, u_int64_t which)
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{
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register u_int64_t a0 __asm__("$16") = (u_int64_t) ent;
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register u_int64_t a1 __asm__("$17") = which;
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__asm__ __volatile__ (
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"call_pal 0x34 #PAL_OSF1_wrent"
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: "=r" (a0), "=r" (a1)
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: "0" (a0), "1" (a1)
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: "$1", "$22", "$23", "$24", "$25");
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}
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static __inline u_int64_t
|
|
alpha_pal_swpipl(u_int64_t newipl)
|
|
{
|
|
register u_int64_t a0 __asm__("$16") = newipl;
|
|
register u_int64_t v0 __asm__("$0");
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x35 #PAL_OSF1_swpipl"
|
|
: "=r" (v0), "=r" (a0)
|
|
: "1" (a0)
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
return v0;
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
alpha_pal_rdps(void)
|
|
{
|
|
register u_int64_t v0 __asm__("$0");
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x36 #PAL_OSF1_rdps"
|
|
: "=r" (v0)
|
|
:
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
return v0;
|
|
}
|
|
|
|
static __inline void
|
|
alpha_pal_wrusp(u_int64_t usp)
|
|
{
|
|
register u_int64_t a0 __asm__("$16") = usp;
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x38 #PAL_wrusp"
|
|
: "=r" (a0)
|
|
: "0" (a0)
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
alpha_pal_wrperfmon(u_int64_t arg0, u_int64_t arg1)
|
|
{
|
|
register u_int64_t v0 __asm__("$0");
|
|
register u_int64_t a0 __asm__("$16") = arg0;
|
|
register u_int64_t a1 __asm__("$17") = arg1;
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x39 #PAL_OSF1_wrperfmon"
|
|
: "=r" (a0), "=r" (a1), "=r" (v0)
|
|
: "0" (a0), "1" (a1)
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
return v0;
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
alpha_pal_rdusp(void)
|
|
{
|
|
register u_int64_t v0 __asm__("$0");
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x3a #PAL_OSF1_rdusp"
|
|
: "=r" (v0)
|
|
:
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
return v0;
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
alpha_pal_whami(void)
|
|
{
|
|
register u_int64_t v0 __asm__("$0");
|
|
__asm__ __volatile__ (
|
|
"call_pal 0x3c #PAL_OSF1_whami"
|
|
: "=r" (v0)
|
|
:
|
|
: "$1", "$22", "$23", "$24", "$25");
|
|
return v0;
|
|
}
|
|
|
|
static __inline void
|
|
alpha_pal_imb(void)
|
|
{
|
|
__asm__ __volatile__ ("call_pal 0x86 #PAL_imb");
|
|
}
|
|
|
|
#endif /* __ALPHA_ALPHA_CPU_H__ */
|