87a2f105ee
The QCA955x has more mux interrupts going on - and the AR934x actually does, but I cheated and assigned wlan and pcie to the same interrupt line. They are, there's just a status register mux that I should've been using. Luckily this isn't too bad a change in itself - almost all of the Atheros MIPS configurations use a _BASE file to inherit from. Except PB92, which I should really fix up at some point. The AR934x will use the legacy apb for now until I write its replacement. The QCA955x SoC I'm doing bring-up on will have a separate qca955x_apb.c implementation that includes hooking into IP2/IP3 and doing further interrupt demuxing as appropriate.
33 lines
1.3 KiB
Plaintext
33 lines
1.3 KiB
Plaintext
# $FreeBSD$
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mips/atheros/apb.c optional ar71xx_apb
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mips/atheros/ar71xx_gpio.c optional gpio
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mips/atheros/ar71xx_machdep.c standard
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mips/atheros/ar71xx_ehci.c optional ehci
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mips/atheros/ar71xx_ohci.c optional ohci
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mips/atheros/ar71xx_pci.c optional ar71xx_pci pci
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mips/atheros/ar724x_pci.c optional ar724x_pci pci
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mips/atheros/ar71xx_pci_bus_space.c optional pci
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mips/atheros/ar71xx_spi.c optional ar71xx_spi
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mips/atheros/pcf2123_rtc.c optional pcf2123_rtc ar71xx_spi
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mips/atheros/ar71xx_wdog.c optional ar71xx_wdog
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mips/atheros/if_arge.c optional arge
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mips/atheros/uart_bus_ar71xx.c optional uart_ar71xx
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mips/atheros/uart_cpu_ar71xx.c optional uart_ar71xx
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mips/atheros/uart_bus_ar933x.c optional uart_ar933x
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mips/atheros/uart_cpu_ar933x.c optional uart_ar933x
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mips/atheros/uart_dev_ar933x.c optional uart_ar933x
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mips/atheros/ar71xx_bus_space_reversed.c standard
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mips/mips/intr_machdep.c standard
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mips/mips/tick.c standard
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mips/atheros/ar71xx_setup.c standard
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mips/atheros/ar71xx_chip.c standard
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mips/atheros/ar724x_chip.c standard
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mips/atheros/ar91xx_chip.c standard
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mips/atheros/ar933x_chip.c standard
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mips/atheros/ar934x_chip.c standard
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mips/atheros/qca955x_chip.c standard
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mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom
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dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k
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