373 lines
10 KiB
C
373 lines
10 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/ata/ata-all.h>
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#include <ata_if.h>
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void
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ata_sata_phy_check_events(device_t dev, int port)
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{
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struct ata_channel *ch = device_get_softc(dev);
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u_int32_t error, status;
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if (ata_sata_scr_read(ch, port, ATA_SERROR, &error))
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return;
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/* Check that SError value is sane. */
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if (error == 0xffffffff)
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return;
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/* Clear set error bits/interrupt. */
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if (error)
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ata_sata_scr_write(ch, port, ATA_SERROR, error);
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/* if we have a connection event deal with it */
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if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
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if (bootverbose) {
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if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) {
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device_printf(dev, "PHYRDY change\n");
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} else if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
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((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
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((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
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device_printf(dev, "CONNECT requested\n");
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} else
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device_printf(dev, "DISCONNECT requested\n");
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}
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taskqueue_enqueue(taskqueue_thread, &ch->conntask);
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}
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}
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int
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ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
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{
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if (ch->hw.pm_read != NULL)
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return (ch->hw.pm_read(ch->dev, port, reg, val));
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if (ch->r_io[reg].res) {
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*val = ATA_IDX_INL(ch, reg);
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return (0);
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}
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return (-1);
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}
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int
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ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
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{
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if (ch->hw.pm_write != NULL)
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return (ch->hw.pm_write(ch->dev, port, reg, val));
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if (ch->r_io[reg].res) {
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ATA_IDX_OUTL(ch, reg, val);
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return (0);
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}
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return (-1);
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}
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static int
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ata_sata_connect(struct ata_channel *ch, int port, int quick)
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{
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u_int32_t status;
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int timeout, t;
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/* wait up to 1 second for "connect well" */
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timeout = (quick == 2) ? 0 : 100;
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t = 0;
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while (1) {
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if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
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return (0);
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if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
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((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
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((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
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break;
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if (++t > timeout)
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break;
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ata_udelay(10000);
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}
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if (bootverbose) {
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if (t > timeout) {
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if (port < 0) {
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device_printf(ch->dev, "SATA connect timeout status=%08x\n",
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status);
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} else {
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device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
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port, status);
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}
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} else if (port < 0) {
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device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
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t * 10, status);
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} else {
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device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
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port, t * 10, status);
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}
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}
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/* clear SATA error register */
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ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
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return ((t > timeout) ? 0 : 1);
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}
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int
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ata_sata_phy_reset(device_t dev, int port, int quick)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int loop, retry, sata_rev;
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uint32_t val, val1;
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#ifdef ATA_CAM
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sata_rev = ch->user[port < 0 ? 0 : port].revision;
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if (sata_rev > 0)
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quick = 0;
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#else
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sata_rev = 0;
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#endif
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if (quick) {
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if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
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return (0);
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if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
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ata_sata_scr_write(ch, port, ATA_SCONTROL,
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ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
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ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
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return ata_sata_connect(ch, port, quick);
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}
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}
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if (bootverbose) {
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if (port < 0) {
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device_printf(dev, "hard reset ...\n");
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} else {
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device_printf(dev, "p%d: hard reset ...\n", port);
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}
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}
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if (sata_rev == 1)
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val1 = ATA_SC_SPD_SPEED_GEN1;
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else if (sata_rev == 2)
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val1 = ATA_SC_SPD_SPEED_GEN2;
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else if (sata_rev == 3)
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val1 = ATA_SC_SPD_SPEED_GEN3;
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else
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val1 = 0;
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for (retry = 0; retry < 10; retry++) {
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for (loop = 0; loop < 10; loop++) {
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if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET |
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val1 | ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
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goto fail;
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ata_udelay(100);
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if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
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goto fail;
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if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
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break;
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}
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ata_udelay(5000);
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for (loop = 0; loop < 10; loop++) {
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if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
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ATA_SC_DET_IDLE | val1 | ((ch->pm_level > 0) ? 0 :
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ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
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goto fail;
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ata_udelay(100);
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if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
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goto fail;
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if ((val & ATA_SC_DET_MASK) == 0)
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return ata_sata_connect(ch, port, 0);
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}
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}
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fail:
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/* Clear SATA error register. */
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ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
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if (bootverbose) {
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if (port < 0) {
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device_printf(dev, "hard reset failed\n");
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} else {
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device_printf(dev, "p%d: hard reset failed\n", port);
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}
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}
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return (0);
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}
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int
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ata_sata_setmode(device_t dev, int target, int mode)
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{
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return (min(mode, ATA_UDMA5));
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}
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int
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ata_sata_getrev(device_t dev, int target)
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{
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struct ata_channel *ch = device_get_softc(dev);
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if (ch->r_io[ATA_SSTATUS].res)
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return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4);
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return (0xff);
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}
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int
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ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
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{
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if (request->flags & ATA_R_ATAPI) {
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fis[0] = 0x27; /* host to device */
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fis[1] = 0x80 | (request->unit & 0x0f);
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fis[2] = ATA_PACKET_CMD;
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if (request->flags & (ATA_R_READ | ATA_R_WRITE))
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fis[3] = ATA_F_DMA;
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else {
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fis[5] = request->transfersize;
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fis[6] = request->transfersize >> 8;
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}
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fis[7] = ATA_D_LBA;
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fis[15] = ATA_A_4BIT;
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return 20;
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}
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else {
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fis[0] = 0x27; /* host to device */
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fis[1] = 0x80 | (request->unit & 0x0f);
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fis[2] = request->u.ata.command;
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fis[3] = request->u.ata.feature;
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fis[4] = request->u.ata.lba;
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fis[5] = request->u.ata.lba >> 8;
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fis[6] = request->u.ata.lba >> 16;
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fis[7] = ATA_D_LBA;
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if (!(request->flags & ATA_R_48BIT))
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fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
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fis[8] = request->u.ata.lba >> 24;
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fis[9] = request->u.ata.lba >> 32;
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fis[10] = request->u.ata.lba >> 40;
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fis[11] = request->u.ata.feature >> 8;
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fis[12] = request->u.ata.count;
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fis[13] = request->u.ata.count >> 8;
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fis[15] = ATA_A_4BIT;
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return 20;
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}
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return 0;
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}
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void
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ata_pm_identify(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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u_int32_t pm_chipid, pm_revision, pm_ports;
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int port;
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/* get PM vendor & product data */
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if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
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device_printf(dev, "error getting PM vendor data\n");
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return;
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}
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/* get PM revision data */
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if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
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device_printf(dev, "error getting PM revison data\n");
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return;
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}
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/* get number of HW ports on the PM */
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if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
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device_printf(dev, "error getting PM port info\n");
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return;
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}
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pm_ports &= 0x0000000f;
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/* chip specific quirks */
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switch (pm_chipid) {
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case 0x37261095:
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/* This PM declares 6 ports, while only 5 of them are real.
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* Port 5 is enclosure management bridge port, which has implementation
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* problems, causing probe faults. Hide it for now. */
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device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
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pm_revision, pm_ports);
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pm_ports = 5;
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break;
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case 0x47261095:
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/* This PM declares 7 ports, while only 5 of them are real.
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* Port 5 is some fake "Config Disk" with 640 sectors size,
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* port 6 is enclosure management bridge port.
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* Both fake ports has implementation problems, causing
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* probe faults. Hide them for now. */
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device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
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pm_revision, pm_ports);
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pm_ports = 5;
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break;
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default:
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device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
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pm_chipid, pm_revision, pm_ports);
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}
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/* reset all ports and register if anything connected */
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for (port=0; port < pm_ports; port++) {
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u_int32_t signature;
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if (!ata_sata_phy_reset(dev, port, 1))
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continue;
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/*
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* XXX: I have no idea how to properly wait for PMP port hardreset
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* completion. Without this delay soft reset does not completes
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* successfully.
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*/
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DELAY(1000000);
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signature = ch->hw.softreset(dev, port);
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if (bootverbose)
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device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
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/* figure out whats there */
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switch (signature >> 16) {
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case 0x0000:
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ch->devices |= (ATA_ATA_MASTER << port);
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continue;
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case 0xeb14:
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ch->devices |= (ATA_ATAPI_MASTER << port);
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continue;
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}
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}
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}
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