8a0fd1a7cd
Clocks, GPIO, UART, SD card / eMMC, USB, watchdog, and ethernet are supported. Note that the A83T contains two clusters of four Cortex-A7 CPUs, and only CPUs in first cluster are started for now. Tested on a Sinovoip Banana Pi BPI-M3.
381 lines
9.4 KiB
C
381 lines
9.4 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner AHB clock
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk.h>
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#include "clkdev_if.h"
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#define A10_AHB_CLK_DIV_RATIO (0x3 << 4)
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#define A10_AHB_CLK_DIV_RATIO_SHIFT 4
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#define A13_AHB_CLK_SRC_SEL (0x3 << 6)
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#define A13_AHB_CLK_SRC_SEL_MAX 3
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#define A13_AHB_CLK_SRC_SEL_SHIFT 6
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#define A31_AHB1_PRE_DIV (0x3 << 6)
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#define A31_AHB1_PRE_DIV_SHIFT 6
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#define A31_AHB1_CLK_SRC_SEL (0x3 << 12)
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#define A31_AHB1_CLK_SRC_SEL_PLL6 3
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#define A31_AHB1_CLK_SRC_SEL_MAX 3
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#define A31_AHB1_CLK_SRC_SEL_SHIFT 12
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#define A83T_AHB1_CLK_SRC_SEL (0x3 << 12)
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#define A83T_AHB1_CLK_SRC_SEL_ISPLL(x) ((x) & 0x2)
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#define A83T_AHB1_CLK_SRC_SEL_MAX 3
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#define A83T_AHB1_CLK_SRC_SEL_SHIFT 12
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#define A83T_AHB1_PRE_DIV (0x3 << 6)
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#define A83T_AHB1_PRE_DIV_SHIFT 6
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#define A83T_AHB1_CLK_DIV_RATIO (0x3 << 4)
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#define A83T_AHB1_CLK_DIV_RATIO_SHIFT 4
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#define H3_AHB2_CLK_CFG (0x3 << 0)
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#define H3_AHB2_CLK_CFG_SHIFT 0
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#define H3_AHB2_CLK_CFG_AHB1 0
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#define H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2 1
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#define H3_AHB2_CLK_CFG_MAX 1
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enum aw_ahbclk_type {
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AW_A10_AHB = 1,
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AW_A13_AHB,
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AW_A31_AHB1,
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AW_A83T_AHB1,
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AW_H3_AHB2,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-ahb-clk", AW_A10_AHB },
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{ "allwinner,sun5i-a13-ahb-clk", AW_A13_AHB },
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{ "allwinner,sun6i-a31-ahb1-clk", AW_A31_AHB1 },
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{ "allwinner,sun8i-a83t-ahb1-clk", AW_A83T_AHB1 },
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{ "allwinner,sun8i-h3-ahb2-clk", AW_H3_AHB2 },
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{ NULL, 0 }
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};
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struct aw_ahbclk_sc {
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device_t clkdev;
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bus_addr_t reg;
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enum aw_ahbclk_type type;
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};
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#define AHBCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
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#define AHBCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
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#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
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#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
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static int
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aw_ahbclk_init(struct clknode *clk, device_t dev)
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{
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struct aw_ahbclk_sc *sc;
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uint32_t val, index;
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sc = clknode_get_softc(clk);
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switch (sc->type) {
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case AW_A10_AHB:
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index = 0;
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break;
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case AW_A13_AHB:
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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index = (val & A13_AHB_CLK_SRC_SEL) >>
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A13_AHB_CLK_SRC_SEL_SHIFT;
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break;
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case AW_A31_AHB1:
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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index = (val & A31_AHB1_CLK_SRC_SEL) >>
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A31_AHB1_CLK_SRC_SEL_SHIFT;
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break;
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case AW_A83T_AHB1:
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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index = (val & A83T_AHB1_CLK_SRC_SEL) >>
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A83T_AHB1_CLK_SRC_SEL_SHIFT;
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break;
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case AW_H3_AHB2:
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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index = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
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break;
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default:
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return (ENXIO);
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}
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clknode_init_parent_idx(clk, index);
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return (0);
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}
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static int
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aw_ahbclk_recalc_freq(struct clknode *clk, uint64_t *freq)
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{
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struct aw_ahbclk_sc *sc;
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uint32_t val, src_sel, div, pre_div;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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switch (sc->type) {
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case AW_A31_AHB1:
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div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >>
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A10_AHB_CLK_DIV_RATIO_SHIFT);
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src_sel = (val & A31_AHB1_CLK_SRC_SEL) >>
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A31_AHB1_CLK_SRC_SEL_SHIFT;
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if (src_sel == A31_AHB1_CLK_SRC_SEL_PLL6)
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pre_div = ((val & A31_AHB1_PRE_DIV) >>
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A31_AHB1_PRE_DIV_SHIFT) + 1;
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else
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pre_div = 1;
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break;
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case AW_A83T_AHB1:
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div = 1 << ((val & A83T_AHB1_CLK_DIV_RATIO) >>
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A83T_AHB1_CLK_DIV_RATIO_SHIFT);
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src_sel = (val & A83T_AHB1_CLK_SRC_SEL) >>
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A83T_AHB1_CLK_SRC_SEL_SHIFT;
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if (A83T_AHB1_CLK_SRC_SEL_ISPLL(src_sel))
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pre_div = ((val & A83T_AHB1_PRE_DIV) >>
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A83T_AHB1_PRE_DIV_SHIFT) + 1;
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else
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pre_div = 1;
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break;
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case AW_H3_AHB2:
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src_sel = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
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if (src_sel == H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2)
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div = 2;
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else
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div = 1;
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pre_div = 1;
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break;
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default:
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div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >>
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A10_AHB_CLK_DIV_RATIO_SHIFT);
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pre_div = 1;
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break;
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}
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*freq = *freq / pre_div / div;
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return (0);
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}
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static int
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aw_ahbclk_set_mux(struct clknode *clk, int index)
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{
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struct aw_ahbclk_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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switch (sc->type) {
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case AW_A10_AHB:
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if (index != 0)
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return (ERANGE);
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break;
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case AW_A13_AHB:
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if (index < 0 || index > A13_AHB_CLK_SRC_SEL_MAX)
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return (ERANGE);
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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val &= ~A13_AHB_CLK_SRC_SEL;
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val |= (index << A13_AHB_CLK_SRC_SEL_SHIFT);
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AHBCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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break;
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case AW_A83T_AHB1:
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if (index < 0 || index > A83T_AHB1_CLK_SRC_SEL_MAX)
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return (ERANGE);
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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val &= ~A83T_AHB1_CLK_SRC_SEL;
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val |= (index << A83T_AHB1_CLK_SRC_SEL_SHIFT);
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AHBCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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break;
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case AW_H3_AHB2:
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if (index < 0 || index > H3_AHB2_CLK_CFG)
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return (ERANGE);
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DEVICE_LOCK(sc);
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AHBCLK_READ(sc, &val);
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val &= ~H3_AHB2_CLK_CFG;
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val |= (index << H3_AHB2_CLK_CFG_SHIFT);
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AHBCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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break;
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default:
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return (ENXIO);
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}
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return (0);
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}
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static clknode_method_t aw_ahbclk_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, aw_ahbclk_init),
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CLKNODEMETHOD(clknode_recalc_freq, aw_ahbclk_recalc_freq),
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CLKNODEMETHOD(clknode_set_mux, aw_ahbclk_set_mux),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(aw_ahbclk_clknode, aw_ahbclk_clknode_class,
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aw_ahbclk_clknode_methods, sizeof(struct aw_ahbclk_sc), clknode_class);
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static int
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aw_ahbclk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner AHB Clock");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_ahbclk_attach(device_t dev)
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{
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struct clknode_init_def def;
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struct aw_ahbclk_sc *sc;
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struct clkdom *clkdom;
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struct clknode *clk;
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clk_t clk_parent;
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bus_addr_t paddr;
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bus_size_t psize;
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phandle_t node;
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int error, ncells, i;
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node = ofw_bus_get_node(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return (ENXIO);
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}
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0) {
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device_printf(dev, "cannot get clock count\n");
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return (error);
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}
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clkdom = clkdom_create(dev);
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memset(&def, 0, sizeof(def));
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def.id = 1;
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def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP,
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M_WAITOK);
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for (i = 0; i < ncells; i++) {
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error = clk_get_by_ofw_index(dev, i, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", i);
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goto fail;
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}
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def.parent_names[i] = clk_get_name(clk_parent);
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clk_release(clk_parent);
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}
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def.parent_cnt = ncells;
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error = clk_parse_ofw_clk_name(dev, node, &def.name);
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if (error != 0) {
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device_printf(dev, "cannot parse clock name\n");
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error = ENXIO;
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goto fail;
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}
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clk = clknode_create(clkdom, &aw_ahbclk_clknode_class, &def);
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if (clk == NULL) {
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device_printf(dev, "cannot create clknode\n");
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error = ENXIO;
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goto fail;
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}
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sc = clknode_get_softc(clk);
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sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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sc->reg = paddr;
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sc->clkdev = device_get_parent(dev);
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clknode_register(clkdom, clk);
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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error = ENXIO;
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goto fail;
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}
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if (bootverbose)
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clkdom_dump(clkdom);
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return (0);
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fail:
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return (error);
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}
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static device_method_t aw_ahbclk_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_ahbclk_probe),
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DEVMETHOD(device_attach, aw_ahbclk_attach),
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DEVMETHOD_END
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};
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static driver_t aw_ahbclk_driver = {
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"aw_ahbclk",
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aw_ahbclk_methods,
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0
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};
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static devclass_t aw_ahbclk_devclass;
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EARLY_DRIVER_MODULE(aw_ahbclk, simplebus, aw_ahbclk_driver,
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aw_ahbclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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