2c96ac7a39
where possible. In the places that doesn't work (multi-line inline asm, and places where the old armv4 cpufuncs mechanism is used), annotate the accesses with a comment that includes SCTLR. Now a grep -i sctlr can find all the system control register manipulations. No functional changes.
484 lines
12 KiB
ArmAsm
484 lines
12 KiB
ArmAsm
/* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
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/*-
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* Copyright 2011 Semihalf
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "assym.s"
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#include <sys/syscall.h>
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#include <machine/asm.h>
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#include <machine/armreg.h>
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#include <machine/cpuconf.h>
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#include <machine/pte-v4.h>
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__FBSDID("$FreeBSD$");
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/* 2K initial stack is plenty, it is only used by initarm() */
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#define INIT_ARM_STACK_SIZE 2048
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov tmp, tmp /* wait for it to complete */ ;\
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CPWAIT_BRANCH /* branch to next insn */
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/*
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* This is for libkvm, and should be the address of the beginning
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* of the kernel text segment (not necessarily the same as kernbase).
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*
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* These are being phased out. Newer copies of libkvm don't need these
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* values as the information is added to the core file by inspecting
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* the running kernel.
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*/
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.text
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.align 2
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#ifdef PHYSADDR
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.globl kernbase
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.set kernbase,KERNBASE
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.globl physaddr
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.set physaddr,PHYSADDR
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#endif
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/*
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* On entry for FreeBSD boot ABI:
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* r0 - metadata pointer or 0 (boothowto on AT91's boot2)
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* r1 - if (r0 == 0) then metadata pointer
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* On entry for Linux boot ABI:
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* r0 - 0
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* r1 - machine type (passed as arg2 to initarm)
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* r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
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*
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* For both types of boot we gather up the args, put them in a struct arm_boot_params
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* structure and pass that to initarm.
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*/
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.globl btext
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btext:
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ASENTRY_NP(_start)
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STOP_UNWINDING /* Can't unwind into the bootloader! */
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mov r9, r0 /* 0 or boot mode from boot2 */
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mov r8, r1 /* Save Machine type */
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mov ip, r2 /* Save meta data */
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mov fp, r3 /* Future expansion */
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/* Make sure interrupts are disabled. */
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mrs r7, cpsr
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orr r7, r7, #(PSR_I | PSR_F)
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msr cpsr_c, r7
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#if defined (FLASHADDR) && defined(LOADERRAMADDR)
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/*
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* Sanity check the configuration.
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* FLASHADDR and LOADERRAMADDR depend on PHYSADDR in some cases.
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* ARMv4 and ARMv5 make assumptions on where they are loaded.
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* TODO: Fix the ARMv4/v5 case.
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*/
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#ifndef PHYSADDR
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#error PHYSADDR must be defined for this configuration
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#endif
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/* Check if we're running from flash. */
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ldr r7, =FLASHADDR
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/*
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* If we're running with MMU disabled, test against the
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* physical address instead.
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*/
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mrc CP15_SCTLR(r2)
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ands r2, r2, #CPU_CONTROL_MMU_ENABLE
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ldreq r6, =PHYSADDR
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ldrne r6, =LOADERRAMADDR
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cmp r7, r6
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bls flash_lower
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cmp r7, pc
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bhi from_ram
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b do_copy
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flash_lower:
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cmp r6, pc
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bls from_ram
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do_copy:
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ldr r7, =KERNBASE
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adr r1, _start
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ldr r0, Lreal_start
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ldr r2, Lend
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sub r2, r2, r0
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sub r0, r0, r7
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add r0, r0, r6
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mov r4, r0
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bl memcpy
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ldr r0, Lram_offset
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add pc, r4, r0
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Lram_offset: .word from_ram-_C_LABEL(_start)
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from_ram:
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nop
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#endif
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disable_mmu:
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/* Disable MMU for a while */
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mrc CP15_SCTLR(r2)
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bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
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CPU_CONTROL_WBUF_ENABLE)
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bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
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bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
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mcr CP15_SCTLR(r2)
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nop
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nop
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nop
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CPWAIT(r0)
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Lunmapped:
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/*
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* Build page table from scratch.
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*/
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/*
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* Figure out the physical address we're loaded at by assuming this
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* entry point code is in the first L1 section and so if we clear the
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* offset bits of the pc that will give us the section-aligned load
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* address, which remains in r5 throughout all the following code.
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*/
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ldr r2, =(L1_S_OFFSET)
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bic r5, pc, r2
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/* Find the delta between VA and PA, result stays in r0 throughout. */
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adr r0, Lpagetable
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bl translate_va_to_pa
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/*
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* First map the entire 4GB address space as VA=PA. It's mapped as
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* normal (cached) memory because it's for things like accessing the
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* parameters passed in from the bootloader, which might be at any
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* physical address, different for every platform.
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*/
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mov r1, #0
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mov r2, #0
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mov r3, #4096
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bl build_pagetables
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/*
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* Next we do 64MiB starting at the physical load address, mapped to
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* the VA the kernel is linked for.
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*/
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mov r1, r5
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ldr r2, =(KERNVIRTADDR)
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mov r3, #64
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bl build_pagetables
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/* Create a device mapping for early_printf if specified. */
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#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
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ldr r1, =SOCDEV_PA
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ldr r2, =SOCDEV_VA
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mov r3, #1
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bl build_device_pagetables
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#endif
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/*
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* Enable MMU.
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*/
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mrc CP15_SCTLR(r0)
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orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
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mcr CP15_SCTLR(r0)
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nop
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nop
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nop
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CPWAIT(r0)
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/* Transition the PC from physical to virtual addressing. */
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ldr pc,=mmu_done
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mmu_done:
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nop
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adr r1, .Lstart
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ldmia r1, {r1, r2, sp} /* Set initial stack and */
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sub r2, r2, r1 /* get zero init data */
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mov r3, #0
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.L1:
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str r3, [r1], #0x0004 /* get zero init data */
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subs r2, r2, #4
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bgt .L1
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virt_done:
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mov r1, #28 /* loader info size is 28 bytes also second arg */
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subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
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mov r0, sp /* loader info pointer is first arg */
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bic sp, sp, #7 /* align stack to 8 bytes */
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str r1, [r0] /* Store length of loader info */
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str r9, [r0, #4] /* Store r0 from boot loader */
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str r8, [r0, #8] /* Store r1 from boot loader */
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str ip, [r0, #12] /* store r2 from boot loader */
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str fp, [r0, #16] /* store r3 from boot loader */
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str r5, [r0, #20] /* store the physical address */
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adr r4, Lpagetable /* load the pagetable address */
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ldr r5, [r4, #4]
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str r5, [r0, #24] /* store the pagetable address */
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mov fp, #0 /* trace back starts here */
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bl _C_LABEL(initarm) /* Off we go */
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/* init arm will return the new stack pointer. */
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mov sp, r0
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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adr r0, .Lmainreturned
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b _C_LABEL(panic)
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/* NOTREACHED */
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END(_start)
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#define VA_TO_PA_POINTER(name, table) \
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name: ;\
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.word . ;\
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.word table
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/*
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* Returns the physical address of a magic va to pa pointer.
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* r0 - The pagetable data pointer. This must be built using the
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* VA_TO_PA_POINTER macro.
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* e.g.
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* VA_TO_PA_POINTER(Lpagetable, pagetable)
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* ...
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* adr r0, Lpagetable
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* bl translate_va_to_pa
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* r0 will now contain the physical address of pagetable
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* r1, r2 - Trashed
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*/
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translate_va_to_pa:
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ldr r1, [r0]
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sub r2, r1, r0
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/* At this point: r2 = VA - PA */
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/*
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* Find the physical address of the table. After these two
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* instructions:
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* r1 = va(pagetable)
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*
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* r0 = va(pagetable) - (VA - PA)
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* = va(pagetable) - VA + PA
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* = pa(pagetable)
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*/
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ldr r1, [r0, #4]
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sub r0, r1, r2
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RET
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/*
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* Builds the page table
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* r0 - The table base address
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* r1 - The physical address (trashed)
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* r2 - The virtual address (trashed)
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* r3 - The number of 1MiB sections
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* r4 - Trashed
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*
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* Addresses must be 1MiB aligned
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*/
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build_device_pagetables:
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ldr r4, =(L1_TYPE_S|L1_S_AP(AP_KRW))
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b 1f
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build_pagetables:
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/* Set the required page attributed */
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ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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1:
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orr r1, r4
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/* Move the virtual address to the correct bit location */
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lsr r2, #(L1_S_SHIFT - 2)
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mov r4, r3
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2:
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str r1, [r0, r2]
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add r2, r2, #4
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add r1, r1, #(L1_S_SIZE)
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adds r4, r4, #-1
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bhi 2b
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RET
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VA_TO_PA_POINTER(Lpagetable, pagetable)
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Lreal_start:
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.word _start
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Lend:
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.word _edata
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.Lstart:
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.word _edata
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.word _ebss
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.word svcstk + INIT_ARM_STACK_SIZE
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.Lvirt_done:
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.word virt_done
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.Lmainreturned:
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.asciz "main() returned"
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.align 2
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.bss
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svcstk:
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.space INIT_ARM_STACK_SIZE
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/*
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* Memory for the initial pagetable. We are unable to place this in
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* the bss as this will be cleared after the table is loaded.
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*/
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.section ".init_pagetable"
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.align 14 /* 16KiB aligned */
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pagetable:
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.space L1_TABLE_SIZE
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.text
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.align 2
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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ENTRY_NP(cpu_halt)
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mrs r2, cpsr
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bic r2, r2, #(PSR_MODE)
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orr r2, r2, #(PSR_SVC32_MODE)
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orr r2, r2, #(PSR_I | PSR_F)
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msr cpsr_fsxc, r2
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ldr r4, .Lcpu_reset_address
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ldr r4, [r4]
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ldr r0, .Lcpufuncs
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mov lr, pc
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ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
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mov lr, pc
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ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
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/*
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* Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
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* necessary.
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*/
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ldr r1, .Lcpu_reset_needs_v4_MMU_disable
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ldr r1, [r1]
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cmp r1, #0
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mov r2, #0
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/*
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* MMU & IDC off, 32 bit program & data space
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* Hurl ourselves into the ROM
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*/
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mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
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mcr CP15_SCTLR(r0)
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mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
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mov pc, r4
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/*
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* _cpu_reset_address contains the address to branch to, to complete
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* the cpu reset after turning the MMU off
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* This variable is provided by the hardware specific code
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*/
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.Lcpu_reset_address:
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.word _C_LABEL(cpu_reset_address)
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/*
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* cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
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* v4 MMU disable instruction needs executing... it is an illegal instruction
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* on f.e. ARM6/7 that locks up the computer in an endless illegal
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* instruction / data-abort / reset loop.
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*/
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.Lcpu_reset_needs_v4_MMU_disable:
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.word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
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END(cpu_halt)
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/*
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* setjump + longjmp
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*/
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ENTRY(setjmp)
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stmia r0, {r4-r14}
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mov r0, #0x00000000
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RET
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END(setjmp)
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ENTRY(longjmp)
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ldmia r0, {r4-r14}
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mov r0, #0x00000001
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RET
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END(longjmp)
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.data
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.global _C_LABEL(esym)
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_C_LABEL(esym): .word _C_LABEL(end)
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ENTRY_NP(abort)
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b _C_LABEL(abort)
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END(abort)
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ENTRY_NP(sigcode)
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mov r0, sp
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add r0, r0, #SIGF_UC
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/*
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* Call the sigreturn system call.
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*
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* We have to load r7 manually rather than using
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* "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
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* correct. Using the alternative places esigcode at the address
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* of the data rather than the address one past the data.
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*/
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ldr r7, [pc, #12] /* Load SYS_sigreturn */
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swi SYS_sigreturn
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/* Well if that failed we better exit quick ! */
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ldr r7, [pc, #8] /* Load SYS_exit */
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swi SYS_exit
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/* Branch back to retry SYS_sigreturn */
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b . - 16
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END(sigcode)
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.word SYS_sigreturn
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.word SYS_exit
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.align 2
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.global _C_LABEL(esigcode)
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_C_LABEL(esigcode):
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.data
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.global szsigcode
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szsigcode:
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.long esigcode-sigcode
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/* End of locore.S */
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