455fa6518a
This update brings few features:
o Support for the setmaster/dropmaster ioctls. For instance, they
are used to run multiple X servers simultaneously.
o Support for minor devices. The only user-visible change is a new
entry in /dev/dri but it is useless at the moment. This is a
first step to support render nodes [1].
The main benefit is to greatly reduce the diff with Linux (at the
expense of an unreadable commit diff). Hopefully, next upgrades will be
easier.
No updates were made to the drivers, beside adapting them to API
changes.
[1] https://en.wikipedia.org/wiki/Direct_Rendering_Manager#Render_nodes
Tested by: Many people
MFC after: 1 month
Relnotes: yes
258 lines
7.0 KiB
C
258 lines
7.0 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Jerome Glisse
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/drm2/drmP.h>
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#include <dev/drm2/radeon/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#define RADEON_BENCHMARK_COPY_BLIT 1
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#define RADEON_BENCHMARK_COPY_DMA 0
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#define RADEON_BENCHMARK_ITERATIONS 1024
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#define RADEON_BENCHMARK_COMMON_MODES_N 17
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static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
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uint64_t saddr, uint64_t daddr,
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int flag, int n)
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{
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unsigned long start_jiffies;
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unsigned long end_jiffies;
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struct radeon_fence *fence = NULL;
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int i, r;
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start_jiffies = jiffies;
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for (i = 0; i < n; i++) {
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switch (flag) {
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case RADEON_BENCHMARK_COPY_DMA:
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r = radeon_copy_dma(rdev, saddr, daddr,
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size / RADEON_GPU_PAGE_SIZE,
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&fence);
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break;
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case RADEON_BENCHMARK_COPY_BLIT:
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r = radeon_copy_blit(rdev, saddr, daddr,
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size / RADEON_GPU_PAGE_SIZE,
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&fence);
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break;
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default:
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DRM_ERROR("Unknown copy method\n");
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r = -EINVAL;
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}
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if (r)
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goto exit_do_move;
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r = radeon_fence_wait(fence, false);
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if (r)
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goto exit_do_move;
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radeon_fence_unref(&fence);
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}
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end_jiffies = jiffies;
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r = jiffies_to_msecs(end_jiffies - start_jiffies);
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exit_do_move:
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if (fence)
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radeon_fence_unref(&fence);
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return r;
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}
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static void radeon_benchmark_log_results(int n, unsigned size,
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unsigned int time,
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unsigned sdomain, unsigned ddomain,
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char *kind)
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{
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unsigned int throughput = (n * (size >> 10)) / time;
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DRM_INFO("radeon: %s %u bo moves of %u kB from"
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" %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
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kind, n, size >> 10, sdomain, ddomain, time,
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throughput * 8, throughput);
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}
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static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
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unsigned sdomain, unsigned ddomain)
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{
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struct radeon_bo *dobj = NULL;
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struct radeon_bo *sobj = NULL;
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uint64_t saddr, daddr;
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int r, n;
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int time;
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n = RADEON_BENCHMARK_ITERATIONS;
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, NULL, &sobj);
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if (r) {
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goto out_cleanup;
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}
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r = radeon_bo_reserve(sobj, false);
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if (unlikely(r != 0))
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goto out_cleanup;
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r = radeon_bo_pin(sobj, sdomain, &saddr);
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radeon_bo_unreserve(sobj);
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if (r) {
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goto out_cleanup;
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}
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, NULL, &dobj);
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if (r) {
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goto out_cleanup;
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}
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r = radeon_bo_reserve(dobj, false);
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if (unlikely(r != 0))
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goto out_cleanup;
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r = radeon_bo_pin(dobj, ddomain, &daddr);
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radeon_bo_unreserve(dobj);
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if (r) {
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goto out_cleanup;
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}
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/* r100 doesn't have dma engine so skip the test */
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/* also, VRAM-to-VRAM test doesn't make much sense for DMA */
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/* skip it as well if domains are the same */
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if ((rdev->asic->copy.dma) && (sdomain != ddomain)) {
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time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
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RADEON_BENCHMARK_COPY_DMA, n);
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if (time < 0)
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goto out_cleanup;
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if (time > 0)
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radeon_benchmark_log_results(n, size, time,
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sdomain, ddomain, "dma");
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}
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if (rdev->asic->copy.blit) {
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time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
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RADEON_BENCHMARK_COPY_BLIT, n);
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if (time < 0)
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goto out_cleanup;
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if (time > 0)
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radeon_benchmark_log_results(n, size, time,
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sdomain, ddomain, "blit");
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}
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out_cleanup:
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if (sobj) {
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r = radeon_bo_reserve(sobj, false);
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if (likely(r == 0)) {
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radeon_bo_unpin(sobj);
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radeon_bo_unreserve(sobj);
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}
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radeon_bo_unref(&sobj);
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}
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if (dobj) {
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r = radeon_bo_reserve(dobj, false);
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if (likely(r == 0)) {
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radeon_bo_unpin(dobj);
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radeon_bo_unreserve(dobj);
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}
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radeon_bo_unref(&dobj);
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}
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if (r) {
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DRM_ERROR("Error while benchmarking BO move.\n");
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}
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}
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void radeon_benchmark(struct radeon_device *rdev, int test_number)
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{
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int i;
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int common_modes[RADEON_BENCHMARK_COMMON_MODES_N] = {
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640 * 480 * 4,
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720 * 480 * 4,
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800 * 600 * 4,
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848 * 480 * 4,
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1024 * 768 * 4,
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1152 * 768 * 4,
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1280 * 720 * 4,
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1280 * 800 * 4,
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1280 * 854 * 4,
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1280 * 960 * 4,
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1280 * 1024 * 4,
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1440 * 900 * 4,
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1400 * 1050 * 4,
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1680 * 1050 * 4,
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1600 * 1200 * 4,
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1920 * 1080 * 4,
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1920 * 1200 * 4
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};
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switch (test_number) {
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case 1:
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/* simple test, VRAM to GTT and GTT to VRAM */
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radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_DOMAIN_VRAM);
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radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_GTT);
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break;
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case 2:
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/* simple test, VRAM to VRAM */
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radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_VRAM);
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break;
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case 3:
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/* GTT to VRAM, buffer size sweep, powers of 2 */
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for (i = 1; i <= 16384; i <<= 1)
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radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_DOMAIN_VRAM);
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break;
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case 4:
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/* VRAM to GTT, buffer size sweep, powers of 2 */
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for (i = 1; i <= 16384; i <<= 1)
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radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_GTT);
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break;
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case 5:
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/* VRAM to VRAM, buffer size sweep, powers of 2 */
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for (i = 1; i <= 16384; i <<= 1)
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radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
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RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_VRAM);
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break;
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case 6:
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/* GTT to VRAM, buffer size sweep, common modes */
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for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
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radeon_benchmark_move(rdev, common_modes[i],
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RADEON_GEM_DOMAIN_GTT,
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RADEON_GEM_DOMAIN_VRAM);
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break;
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case 7:
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/* VRAM to GTT, buffer size sweep, common modes */
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for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
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radeon_benchmark_move(rdev, common_modes[i],
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RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_GTT);
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break;
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case 8:
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/* VRAM to VRAM, buffer size sweep, common modes */
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for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
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radeon_benchmark_move(rdev, common_modes[i],
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RADEON_GEM_DOMAIN_VRAM,
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RADEON_GEM_DOMAIN_VRAM);
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break;
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default:
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DRM_ERROR("Unknown benchmark\n");
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}
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}
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