9bf4c9c1b0
- Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
332 lines
11 KiB
C
332 lines
11 KiB
C
/*-
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* Copyright (c) 2000 Michael Smith
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <contrib/dev/acpica/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include <machine/pci_cfgreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <dev/acpica/acpi_pcibvar.h>
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/* Hooks for the ACPI CA debugging infrastructure. */
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#define _COMPONENT ACPI_BUS
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ACPI_MODULE_NAME("PCI_ACPI")
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struct acpi_hpcib_softc {
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device_t ap_dev;
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ACPI_HANDLE ap_handle;
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int ap_flags;
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int ap_segment; /* analagous to Alpha 'hose' */
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int ap_bus; /* bios-assigned bus number */
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ACPI_BUFFER ap_prt; /* interrupt routing table */
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};
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static int acpi_pcib_acpi_probe(device_t bus);
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static int acpi_pcib_acpi_attach(device_t bus);
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static int acpi_pcib_acpi_resume(device_t bus);
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static int acpi_pcib_read_ivar(device_t dev, device_t child,
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int which, uintptr_t *result);
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static int acpi_pcib_write_ivar(device_t dev, device_t child,
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int which, uintptr_t value);
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static uint32_t acpi_pcib_read_config(device_t dev, int bus, int slot,
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int func, int reg, int bytes);
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static void acpi_pcib_write_config(device_t dev, int bus, int slot,
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int func, int reg, uint32_t data, int bytes);
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static int acpi_pcib_acpi_route_interrupt(device_t pcib,
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device_t dev, int pin);
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static struct resource *acpi_pcib_acpi_alloc_resource(device_t dev,
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device_t child, int type, int *rid,
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u_long start, u_long end, u_long count,
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u_int flags);
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static device_method_t acpi_pcib_acpi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, acpi_pcib_acpi_probe),
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DEVMETHOD(device_attach, acpi_pcib_acpi_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, acpi_pcib_acpi_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, acpi_pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, acpi_pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, acpi_pcib_acpi_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, acpi_pcib_read_config),
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DEVMETHOD(pcib_write_config, acpi_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, acpi_pcib_acpi_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, pcib_release_msi),
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DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
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DEVMETHOD(pcib_release_msix, pcib_release_msix),
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{0, 0}
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};
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static devclass_t pcib_devclass;
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DEFINE_CLASS_0(pcib, acpi_pcib_acpi_driver, acpi_pcib_acpi_methods,
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sizeof(struct acpi_hpcib_softc));
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DRIVER_MODULE(acpi_pcib, acpi, acpi_pcib_acpi_driver, pcib_devclass, 0, 0);
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MODULE_DEPEND(acpi_pcib, acpi, 1, 1, 1);
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static int
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acpi_pcib_acpi_probe(device_t dev)
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{
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static char *pcib_ids[] = { "PNP0A03", NULL };
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if (acpi_disabled("pcib") ||
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ACPI_ID_PROBE(device_get_parent(dev), dev, pcib_ids) == NULL)
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return (ENXIO);
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if (pci_cfgregopen() == 0)
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return (ENXIO);
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device_set_desc(dev, "ACPI Host-PCI bridge");
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return (0);
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}
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static int
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acpi_pcib_acpi_attach(device_t dev)
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{
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struct acpi_hpcib_softc *sc;
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ACPI_STATUS status;
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u_int addr, slot, func, busok;
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uint8_t busno;
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ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
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sc = device_get_softc(dev);
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sc->ap_dev = dev;
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sc->ap_handle = acpi_get_handle(dev);
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/*
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* Get our base bus number by evaluating _BBN.
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* If this doesn't work, we assume we're bus number 0.
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*
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* XXX note that it may also not exist in the case where we are
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* meant to use a private configuration space mechanism for this bus,
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* so we should dig out our resources and check to see if we have
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* anything like that. How do we do this?
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* XXX If we have the requisite information, and if we don't think the
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* default PCI configuration space handlers can deal with this bus,
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* we should attach our own handler.
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* XXX invoke _REG on this for the PCI config space address space?
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* XXX It seems many BIOS's with multiple Host-PCI bridges do not set
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* _BBN correctly. They set _BBN to zero for all bridges. Thus,
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* if _BBN is zero and pcib0 already exists, we try to read our
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* bus number from the configuration registers at address _ADR.
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*/
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status = acpi_GetInteger(sc->ap_handle, "_BBN", &sc->ap_bus);
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if (ACPI_FAILURE(status)) {
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if (status != AE_NOT_FOUND) {
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device_printf(dev, "could not evaluate _BBN - %s\n",
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AcpiFormatException(status));
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return_VALUE (ENXIO);
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} else {
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/* If it's not found, assume 0. */
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sc->ap_bus = 0;
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}
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}
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/*
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* If the bus is zero and pcib0 already exists, read the bus number
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* via PCI config space.
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*/
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busok = 1;
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if (sc->ap_bus == 0 && devclass_get_device(pcib_devclass, 0) != dev) {
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busok = 0;
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status = acpi_GetInteger(sc->ap_handle, "_ADR", &addr);
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if (ACPI_FAILURE(status)) {
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if (status != AE_NOT_FOUND) {
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device_printf(dev, "could not evaluate _ADR - %s\n",
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AcpiFormatException(status));
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return_VALUE (ENXIO);
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} else
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device_printf(dev, "couldn't find _ADR\n");
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} else {
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/* XXX: We assume bus 0. */
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slot = ACPI_ADR_PCI_SLOT(addr);
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func = ACPI_ADR_PCI_FUNC(addr);
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if (bootverbose)
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device_printf(dev, "reading config registers from 0:%d:%d\n",
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slot, func);
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if (host_pcib_get_busno(pci_cfgregread, 0, slot, func, &busno) == 0)
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device_printf(dev, "couldn't read bus number from cfg space\n");
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else {
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sc->ap_bus = busno;
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busok = 1;
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}
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}
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}
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/*
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* If nothing else worked, hope that ACPI at least lays out the
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* host-PCI bridges in order and that as a result our unit number
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* is actually our bus number. There are several reasons this
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* might not be true.
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*/
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if (busok == 0) {
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sc->ap_bus = device_get_unit(dev);
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device_printf(dev, "trying bus number %d\n", sc->ap_bus);
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}
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/*
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* Get our segment number by evaluating _SEG
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* It's OK for this to not exist.
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*/
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status = acpi_GetInteger(sc->ap_handle, "_SEG", &sc->ap_segment);
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if (ACPI_FAILURE(status)) {
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if (status != AE_NOT_FOUND) {
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device_printf(dev, "could not evaluate _SEG - %s\n",
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AcpiFormatException(status));
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return_VALUE (ENXIO);
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}
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/* If it's not found, assume 0. */
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sc->ap_segment = 0;
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}
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return (acpi_pcib_attach(dev, &sc->ap_prt, sc->ap_bus));
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}
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static int
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acpi_pcib_acpi_resume(device_t dev)
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{
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return (acpi_pcib_resume(dev));
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}
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/*
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* Support for standard PCI bridge ivars.
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*/
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static int
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acpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct acpi_hpcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = sc->ap_bus;
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return (0);
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case ACPI_IVAR_HANDLE:
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*result = (uintptr_t)sc->ap_handle;
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return (0);
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case ACPI_IVAR_FLAGS:
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*result = (uintptr_t)sc->ap_flags;
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return (0);
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}
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return (ENOENT);
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}
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static int
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acpi_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct acpi_hpcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->ap_bus = value;
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return (0);
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case ACPI_IVAR_HANDLE:
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sc->ap_handle = (ACPI_HANDLE)value;
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return (0);
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case ACPI_IVAR_FLAGS:
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sc->ap_flags = (int)value;
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return (0);
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}
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return (ENOENT);
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}
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static uint32_t
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acpi_pcib_read_config(device_t dev, int bus, int slot, int func, int reg,
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int bytes)
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{
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return (pci_cfgregread(bus, slot, func, reg, bytes));
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}
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static void
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acpi_pcib_write_config(device_t dev, int bus, int slot, int func, int reg,
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uint32_t data, int bytes)
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{
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pci_cfgregwrite(bus, slot, func, reg, data, bytes);
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}
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static int
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acpi_pcib_acpi_route_interrupt(device_t pcib, device_t dev, int pin)
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{
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struct acpi_hpcib_softc *sc = device_get_softc(pcib);
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return (acpi_pcib_route_interrupt(pcib, dev, pin, &sc->ap_prt));
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}
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static u_long acpi_host_mem_start = 0x80000000;
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TUNABLE_ULONG("hw.acpi.host_mem_start", &acpi_host_mem_start);
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struct resource *
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acpi_pcib_acpi_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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/*
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* If no memory preference is given, use upper 32MB slot most
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* bioses use for their memory window. Typically other bridges
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* before us get in the way to assert their preferences on memory.
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* Hardcoding like this sucks, so a more MD/MI way needs to be
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* found to do it. This is typically only used on older laptops
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* that don't have pci busses behind pci bridge, so assuming > 32MB
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* is liekly OK.
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*/
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if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
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start = acpi_host_mem_start;
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if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
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start = 0x1000;
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return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
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count, flags));
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}
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