4c2ca0f7c8
doesn't do this is beyond me, but that will be investigated later. This results in programming the chip with the correct frequency, which in turn allows devices to negotiate up to the full 20MB/s.
590 lines
16 KiB
C
590 lines
16 KiB
C
/*-
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* Copyright (c) 2004 Scott Long
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* $NetBSD: esp_sbus.c,v 1.27 2002/12/10 13:44:47 pk Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center; Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/bus.h>
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#include <machine/ofw_machdep.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <sparc64/sbus/sbusvar.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/esp/lsi64854reg.h>
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#include <dev/esp/lsi64854var.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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/* #define ESP_SBUS_DEBUG */
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struct esp_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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struct device *sc_dev;
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int sc_rid;
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struct resource *sc_res;
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bus_space_handle_t sc_regh;
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bus_space_tag_t sc_regt;
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int sc_irqrid;
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struct resource *sc_irqres;
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void *sc_irq;
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struct lsi64854_softc *sc_dma; /* pointer to my DMA */
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int sc_pri; /* SBUS priority */
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};
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static int esp_sbus_probe(device_t);
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static int esp_sbus_attach(device_t);
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static int esp_sbus_detach(device_t);
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static int esp_sbus_suspend(device_t);
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static int esp_sbus_resume(device_t);
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static device_method_t esp_sbus_methods[] = {
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DEVMETHOD(device_probe, esp_sbus_probe),
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DEVMETHOD(device_attach, esp_sbus_attach),
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DEVMETHOD(device_detach, esp_sbus_detach),
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DEVMETHOD(device_suspend, esp_sbus_suspend),
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DEVMETHOD(device_resume, esp_sbus_resume),
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{0, 0}
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};
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static driver_t esp_sbus_driver = {
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"esp",
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esp_sbus_methods,
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sizeof(struct esp_softc)
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};
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static devclass_t esp_devclass;
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DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0);
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/*
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* Functions and the switch for the MI code.
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*/
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static u_char esp_read_reg(struct ncr53c9x_softc *, int);
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static void esp_write_reg(struct ncr53c9x_softc *, int, u_char);
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static int esp_dma_isintr(struct ncr53c9x_softc *);
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static void esp_dma_reset(struct ncr53c9x_softc *);
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static int esp_dma_intr(struct ncr53c9x_softc *);
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static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *,
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int, size_t *);
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static void esp_dma_go(struct ncr53c9x_softc *);
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static void esp_dma_stop(struct ncr53c9x_softc *);
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static int esp_dma_isactive(struct ncr53c9x_softc *);
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static void espattach(struct esp_softc *, struct ncr53c9x_glue *);
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static struct ncr53c9x_glue esp_sbus_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int
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esp_sbus_probe(device_t dev)
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{
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const char *name;
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name = ofw_bus_get_name(dev);
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if (strcmp("SUNW,fas", name) == 0) {
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device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI");
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return (-10);
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}
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return (ENXIO);
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}
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static int
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esp_sbus_attach(device_t dev)
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{
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struct esp_softc *esc = device_get_softc(dev);
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct lsi64854_softc *lsc;
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phandle_t node;
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int burst;
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esc->sc_dev = dev;
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node = ofw_bus_get_node(dev);
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if (OF_getprop(node, "initiator-id", &sc->sc_id,
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sizeof(sc->sc_id)) == -1)
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sc->sc_id = 7;
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if (OF_getprop(node, "clock-frequency", &sc->sc_freq,
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sizeof(sc->sc_freq)) == -1) {
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printf("failed to query OFW for clock-frequency\n");
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sc->sc_freq = sbus_get_clockfreq(dev);
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}
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#ifdef ESP_SBUS_DEBUG
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device_printf(dev, "espattach_sbus: sc_id %d, freq %d\n",
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sc->sc_id, sc->sc_freq);
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#endif
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/*
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* allocate space for dma, in SUNW,fas there are no separate
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* dma devices
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*/
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lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
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if (lsc == NULL) {
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device_printf(dev, "out of memory (lsi64854_softc)\n");
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return (ENOMEM);
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}
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esc->sc_dma = lsc;
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/*
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* fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x)
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*/
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/* Map dma registers */
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lsc->sc_rid = 0;
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if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&lsc->sc_rid, RF_ACTIVE)) == NULL) {
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device_printf(dev, "cannot map dma registers\n");
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free(lsc, M_DEVBUF);
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return (ENXIO);
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}
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lsc->sc_regt = rman_get_bustag(lsc->sc_res);
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lsc->sc_regh = rman_get_bushandle(lsc->sc_res);
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/* Create a parent DMA tag based on this bus */
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if (bus_dma_tag_create(NULL, /* parent */
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PAGE_SIZE, 0, /* algnmnt, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
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0, /* nsegments */
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BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
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0, /* flags */
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NULL, NULL, /* No locking */
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&lsc->sc_parent_dmat)) {
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device_printf(dev, "cannot allocate parent DMA tag\n");
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free(lsc, M_DEVBUF);
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return (ENOMEM);
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}
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burst = sbus_get_burstsz(dev);
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#ifdef ESP_SBUS_DEBUG
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printf("espattach_sbus: burst 0x%x\n", burst);
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#endif
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lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 :
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(burst & SBUS_BURST_16) ? 16 : 0;
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lsc->sc_channel = L64854_CHANNEL_SCSI;
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lsc->sc_client = sc;
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lsc->sc_dev = dev;
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lsi64854_attach(lsc);
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/*
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* map SCSI core registers
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*/
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esc->sc_rid = 1;
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if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&esc->sc_rid, RF_ACTIVE)) == NULL) {
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device_printf(dev, "cannot map scsi core registers\n");
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free(lsc, M_DEVBUF);
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return (ENXIO);
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}
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esc->sc_regt = rman_get_bustag(esc->sc_res);
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esc->sc_regh = rman_get_bushandle(esc->sc_res);
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#if 0
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esc->sc_pri = sa->sa_pri;
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/* add me to the sbus structures */
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esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;
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sbus_establish(&esc->sc_sd, &sc->sc_dev);
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#endif
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espattach(esc, &esp_sbus_glue);
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return (0);
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}
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static int
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esp_sbus_detach(device_t dev)
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{
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struct ncr53c9x_softc *sc;
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struct esp_softc *esc;
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esc = device_get_softc(dev);
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sc = &esc->sc_ncr53c9x;
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return (ncr53c9x_detach(sc, 0));
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}
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static int
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esp_sbus_suspend(device_t dev)
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{
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return (ENXIO);
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}
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static int
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esp_sbus_resume(device_t dev)
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{
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return (ENXIO);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
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{
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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unsigned int uid = 0;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = gluep;
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/* gimme MHz */
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sc->sc_freq /= 1000000;
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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/* XXX spec says it's valid after power up or chip reset */
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uid = NCR_READ_REG(sc, NCR_UID);
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if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */
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sc->sc_rev = NCR_VARIANT_FAS366;
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}
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}
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#ifdef ESP_SBUS_DEBUG
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printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid);
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#endif
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/* limit minsync due to unsolved performance issues */
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sc->sc_maxsync = sc->sc_minsync;
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sc->sc_maxoffset = 15;
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sc->sc_extended_geom = 1;
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/*
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* Alas, we must now modify the value a bit, because it's
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* only valid when can switch on FASTCLK and FASTSCSI bits
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* in config register 3...
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*/
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switch (sc->sc_rev) {
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case NCR_VARIANT_ESP100:
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sc->sc_maxwidth = 0;
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sc->sc_maxxfer = 64 * 1024;
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sc->sc_minsync = 0; /* No synch on old chip? */
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break;
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case NCR_VARIANT_ESP100A:
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sc->sc_maxwidth = 1;
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sc->sc_maxxfer = 64 * 1024;
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/* Min clocks/byte is 5 */
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sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
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break;
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case NCR_VARIANT_ESP200:
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case NCR_VARIANT_FAS366:
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sc->sc_maxwidth = 1;
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sc->sc_maxxfer = 16 * 1024 * 1024;
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/* XXX - do actually set FAST* bits */
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break;
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}
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/* Establish interrupt channel */
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esc->sc_irqrid = 0;
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if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,
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&esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) {
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device_printf(esc->sc_dev, "Cannot allocate interrupt\n");
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return;
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}
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if (bus_setup_intr(esc->sc_dev, esc->sc_irqres,
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INTR_TYPE_BIO|INTR_ENTROPY, ncr53c9x_intr, sc, &esc->sc_irq)) {
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device_printf(esc->sc_dev, "Cannot set up interrupt\n");
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return;
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}
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/* Turn on target selection using the `dma' method */
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if (sc->sc_rev != NCR_VARIANT_FAS366)
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sc->sc_features |= NCR_F_DMASELECT;
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/* Do the common parts of attachment. */
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sc->sc_dev = esc->sc_dev;
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ncr53c9x_attach(sc);
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}
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/*
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* Glue functions.
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*/
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#ifdef ESP_SBUS_DEBUG
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int esp_sbus_debug = 0;
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static struct {
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char *r_name;
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int r_flag;
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} esp__read_regnames [] = {
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{ "TCL", 0}, /* 0/00 */
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{ "TCM", 0}, /* 1/04 */
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{ "FIFO", 0}, /* 2/08 */
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{ "CMD", 0}, /* 3/0c */
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{ "STAT", 0}, /* 4/10 */
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{ "INTR", 0}, /* 5/14 */
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{ "STEP", 0}, /* 6/18 */
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{ "FFLAGS", 1}, /* 7/1c */
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{ "CFG1", 1}, /* 8/20 */
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{ "STAT2", 0}, /* 9/24 */
|
|
{ "CFG4", 1}, /* a/28 */
|
|
{ "CFG2", 1}, /* b/2c */
|
|
{ "CFG3", 1}, /* c/30 */
|
|
{ "-none", 1}, /* d/34 */
|
|
{ "TCH", 1}, /* e/38 */
|
|
{ "TCX", 1}, /* f/3c */
|
|
};
|
|
|
|
static struct {
|
|
char *r_name;
|
|
int r_flag;
|
|
} esp__write_regnames[] = {
|
|
{ "TCL", 1}, /* 0/00 */
|
|
{ "TCM", 1}, /* 1/04 */
|
|
{ "FIFO", 0}, /* 2/08 */
|
|
{ "CMD", 0}, /* 3/0c */
|
|
{ "SELID", 1}, /* 4/10 */
|
|
{ "TIMEOUT", 1}, /* 5/14 */
|
|
{ "SYNCTP", 1}, /* 6/18 */
|
|
{ "SYNCOFF", 1}, /* 7/1c */
|
|
{ "CFG1", 1}, /* 8/20 */
|
|
{ "CCF", 1}, /* 9/24 */
|
|
{ "TEST", 1}, /* a/28 */
|
|
{ "CFG2", 1}, /* b/2c */
|
|
{ "CFG3", 1}, /* c/30 */
|
|
{ "-none", 1}, /* d/34 */
|
|
{ "TCH", 1}, /* e/38 */
|
|
{ "TCX", 1}, /* f/3c */
|
|
};
|
|
#endif
|
|
|
|
u_char
|
|
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
u_char v;
|
|
|
|
v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4);
|
|
#ifdef ESP_SBUS_DEBUG
|
|
if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
|
|
printf("RD:%x <%s> %x\n", reg * 4,
|
|
((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v);
|
|
#endif
|
|
return v;
|
|
}
|
|
|
|
void
|
|
esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
#ifdef ESP_SBUS_DEBUG
|
|
if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
|
|
printf("WR:%x <%s> %x\n", reg * 4,
|
|
((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v);
|
|
#endif
|
|
bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v);
|
|
}
|
|
|
|
int
|
|
esp_dma_isintr(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_ISINTR(esc->sc_dma));
|
|
}
|
|
|
|
void
|
|
esp_dma_reset(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_RESET(esc->sc_dma);
|
|
}
|
|
|
|
int
|
|
esp_dma_intr(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_INTR(esc->sc_dma));
|
|
}
|
|
|
|
int
|
|
esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
|
|
int datain, size_t *dmasize)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize));
|
|
}
|
|
|
|
void
|
|
esp_dma_go(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
DMA_GO(esc->sc_dma);
|
|
}
|
|
|
|
void
|
|
esp_dma_stop(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
uint32_t csr;
|
|
|
|
csr = L64854_GCSR(esc->sc_dma);
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(esc->sc_dma, csr);
|
|
}
|
|
|
|
int
|
|
esp_dma_isactive(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
|
|
|
return (DMA_ISACTIVE(esc->sc_dma));
|
|
}
|