175 lines
5.7 KiB
C
175 lines
5.7 KiB
C
/*-
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#if !defined(__i386__)
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#define VGE_FIXUP_RX
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#endif
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#define VGE_JUMBO_MTU 9000
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#define VGE_IFQ_MAXLEN 64
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#define VGE_TX_DESC_CNT 256
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#define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */
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#define VGE_RING_ALIGN 256
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#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
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#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
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#define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT)
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#define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT)
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#define VGE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
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#define VGE_ADDR_HI(y) ((u_int64_t) (y) >> 32)
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#define VGE_BUFLEN(y) ((y) & 0x7FFF)
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#define VGE_OWN(x) (le32toh((x)->vge_sts) & VGE_RDSTS_OWN)
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#define VGE_RXBYTES(x) ((le32toh((x)->vge_sts) & \
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VGE_RDSTS_BUFSIZ) >> 16)
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#define VGE_MIN_FRAMELEN 60
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#ifdef VGE_FIXUP_RX
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#define VGE_ETHER_ALIGN sizeof(uint32_t)
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#else
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#define VGE_ETHER_ALIGN 0
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#endif
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struct vge_type {
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uint16_t vge_vid;
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uint16_t vge_did;
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char *vge_name;
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};
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struct vge_softc;
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struct vge_dmaload_arg {
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struct vge_softc *sc;
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int vge_idx;
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int vge_maxsegs;
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struct mbuf *vge_m0;
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u_int32_t vge_flags;
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};
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struct vge_list_data {
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struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT];
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struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT];
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int vge_tx_prodidx;
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int vge_rx_prodidx;
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int vge_tx_considx;
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int vge_tx_free;
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bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT];
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bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT];
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bus_dma_tag_t vge_mtag; /* mbuf mapping tag */
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bus_dma_tag_t vge_rx_list_tag;
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bus_dmamap_t vge_rx_list_map;
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struct vge_rx_desc *vge_rx_list;
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bus_addr_t vge_rx_list_addr;
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bus_dma_tag_t vge_tx_list_tag;
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bus_dmamap_t vge_tx_list_map;
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struct vge_tx_desc *vge_tx_list;
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bus_addr_t vge_tx_list_addr;
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};
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struct vge_softc {
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struct arpcom arpcom; /* interface info */
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device_t vge_dev;
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bus_space_handle_t vge_bhandle; /* bus space handle */
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bus_space_tag_t vge_btag; /* bus space tag */
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struct resource *vge_res;
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struct resource *vge_irq;
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void *vge_intrhand;
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device_t vge_miibus;
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bus_dma_tag_t vge_parent_tag;
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bus_dma_tag_t vge_tag;
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u_int8_t vge_unit; /* interface number */
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u_int8_t vge_type;
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int vge_if_flags;
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int vge_rx_consumed;
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int vge_link;
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int vge_camidx;
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struct task vge_txtask;
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struct mtx vge_mtx;
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struct mbuf *vge_head;
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struct mbuf *vge_tail;
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struct vge_list_data vge_ldata;
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int suspended; /* 0 = normal 1 = suspended */
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#ifdef DEVICE_POLLING
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int rxcycles;
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#endif
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u_int32_t saved_maps[5]; /* pci data */
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u_int32_t saved_biosaddr;
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u_int8_t saved_intline;
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u_int8_t saved_cachelnsz;
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u_int8_t saved_lattimer;
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};
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#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
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#define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx)
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#define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_STREAM_4(sc, reg, val) \
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bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val)
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
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#define CSR_SETBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
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#define CSR_SETBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define CSR_SETBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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#define CSR_CLRBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
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#define CSR_CLRBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#define CSR_CLRBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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#define VGE_TIMEOUT 10000
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