ca20f8ec29
o Replace __riscv64 with (__riscv && __riscv_xlen == 64) This is required to support new GCC 7.1 compiler. This is compatible with current GCC 6.1 compiler. RISC-V is extensible ISA and the idea here is to have built-in define per each extension, so together with __riscv we will have some subset of these as well (depending on -march string passed to compiler): __riscv_compressed __riscv_atomic __riscv_mul __riscv_div __riscv_muldiv __riscv_fdiv __riscv_fsqrt __riscv_float_abi_soft __riscv_float_abi_single __riscv_float_abi_double __riscv_cmodel_medlow __riscv_cmodel_medany __riscv_cmodel_pic __riscv_xlen Reviewed by: ngie Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11901
155 lines
4.1 KiB
C
155 lines
4.1 KiB
C
/*-
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Rui Paulo under sponsorship from the
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* FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/ptrace.h>
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#include <err.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include "_libproc.h"
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int
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proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)
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{
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struct reg regs;
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if (phdl->status == PS_DEAD || phdl->status == PS_UNDEAD ||
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phdl->status == PS_IDLE) {
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errno = ENOENT;
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return (-1);
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}
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memset(®s, 0, sizeof(regs));
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if (ptrace(PT_GETREGS, proc_getpid(phdl), (caddr_t)®s, 0) < 0)
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return (-1);
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switch (reg) {
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case REG_PC:
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#if defined(__aarch64__)
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*regvalue = regs.elr;
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#elif defined(__amd64__)
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*regvalue = regs.r_rip;
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#elif defined(__arm__)
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*regvalue = regs.r_pc;
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#elif defined(__i386__)
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*regvalue = regs.r_eip;
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#elif defined(__mips__)
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*regvalue = regs.r_regs[PC];
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#elif defined(__powerpc__)
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*regvalue = regs.pc;
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#elif defined(__riscv)
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*regvalue = regs.sepc;
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#endif
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break;
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case REG_SP:
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#if defined(__aarch64__)
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*regvalue = regs.sp;
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#elif defined(__amd64__)
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*regvalue = regs.r_rsp;
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#elif defined(__arm__)
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*regvalue = regs.r_sp;
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#elif defined(__i386__)
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*regvalue = regs.r_esp;
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#elif defined(__mips__)
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*regvalue = regs.r_regs[SP];
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#elif defined(__powerpc__)
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*regvalue = regs.fixreg[1];
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#elif defined(__riscv)
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*regvalue = regs.sp;
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#endif
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break;
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default:
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DPRINTFX("ERROR: no support for reg number %d", reg);
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return (-1);
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}
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return (0);
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}
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int
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proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)
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{
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struct reg regs;
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if (phdl->status == PS_DEAD || phdl->status == PS_UNDEAD ||
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phdl->status == PS_IDLE) {
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errno = ENOENT;
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return (-1);
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}
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if (ptrace(PT_GETREGS, proc_getpid(phdl), (caddr_t)®s, 0) < 0)
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return (-1);
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switch (reg) {
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case REG_PC:
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#if defined(__aarch64__)
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regs.elr = regvalue;
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#elif defined(__amd64__)
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regs.r_rip = regvalue;
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#elif defined(__arm__)
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regs.r_pc = regvalue;
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#elif defined(__i386__)
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regs.r_eip = regvalue;
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#elif defined(__mips__)
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regs.r_regs[PC] = regvalue;
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#elif defined(__powerpc__)
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regs.pc = regvalue;
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#elif defined(__riscv)
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regs.sepc = regvalue;
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#endif
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break;
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case REG_SP:
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#if defined(__aarch64__)
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regs.sp = regvalue;
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#elif defined(__amd64__)
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regs.r_rsp = regvalue;
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#elif defined(__arm__)
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regs.r_sp = regvalue;
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#elif defined(__i386__)
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regs.r_esp = regvalue;
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#elif defined(__mips__)
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regs.r_regs[PC] = regvalue;
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#elif defined(__powerpc__)
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regs.fixreg[1] = regvalue;
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#elif defined(__riscv)
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regs.sp = regvalue;
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#endif
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break;
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default:
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DPRINTFX("ERROR: no support for reg number %d", reg);
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return (-1);
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}
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if (ptrace(PT_SETREGS, proc_getpid(phdl), (caddr_t)®s, 0) < 0)
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return (-1);
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return (0);
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}
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