3e4756a1ce
The hope is to make the sequencer and kernel code share this file, but some work on our sequencer assembler will be needed first.
515 lines
13 KiB
C
515 lines
13 KiB
C
/*
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* Aic7xxx register and scratch ram definitions.
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*
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* Copyright (c) 1994, 1995 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Justin T. Gibbs.
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* 4. Modifications may be freely made to this file if the above conditions
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* are met.
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*
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* $Id$
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*/
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/*
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* This header should be shared by the sequencer code and the kernel
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* level driver. Unfortuanetly I haven't mangled the sequencer assembler
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* into using cpp yet. Someday...
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*
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* All page numbers refer to the Adaptec AIC-7770 Data Book availible from
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* Adaptec's Technical Documents Department 1-800-934-2766
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*/
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/*
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* SCSI Sequence Control (p. 3-11).
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* Each bit, when set starts a specific SCSI sequence on the bus
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*/
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#define SCSISEQ 0x000
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#define TEMODEO 0x80
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#define ENSELO 0x40
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#define ENSELI 0x20
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#define ENRSELI 0x10
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#define ENAUTOATNO 0x08
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#define ENAUTOATNI 0x04
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#define ENAUTOATNP 0x02
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#define SCSIRSTO 0x01
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/*
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* SCSI Transfer Control 0 Register (pp. 3-13).
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* Controls the SCSI module data path.
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*/
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#define SXFRCTL0 0x001
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#define DFON 0x80
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#define DFPEXP 0x40
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#define ULTRAEN 0x20
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#define CLRSTCNT 0x10
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#define SPIOEN 0x08
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#define SCAMEN 0x04
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#define CLRCHN 0x02
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/* UNUSED 0x01 */
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/*
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* SCSI Transfer Control 1 Register (pp. 3-14,15).
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* Controls the SCSI module data path.
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*/
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#define SXFRCTL1 0x002
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#define BITBUCKET 0x80
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#define SWRAPEN 0x40
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#define ENSPCHK 0x20
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#define STIMESEL 0x18
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#define ENSTIMER 0x04
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#define ACTNEGEN 0x02
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#define STPWEN 0x01 /* Powered Termination */
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/*
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* SCSI Interrrupt Mode 1 (pp. 3-28,29).
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* Set bits in this register enable the corresponding
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* interrupt source.
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*/
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#define SIMODE1 0x011
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#define ENSELTIMO 0x80
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#define ENATNTARG 0x40
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#define ENSCSIRST 0x20
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#define ENPHASEMIS 0x10
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#define ENBUSFREE 0x08
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#define ENSCSIPERR 0x04
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#define ENPHASECHG 0x02
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#define ENREQINIT 0x01
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/*
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* SCSI Control Signal Read Register (p. 3-15).
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* Reads the actual state of the SCSI bus pins
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*/
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#define SCSISIGI 0x003
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#define CDI 0x80
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#define IOI 0x40
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#define MSGI 0x20
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#define ATNI 0x10
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#define SELI 0x08
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#define BSYI 0x04
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#define REQI 0x02
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#define ACKI 0x01
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/*
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* SCSI Contol Signal Write Register (p. 3-16).
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* Writing to this register modifies the control signals on the bus. Only
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* those signals that are allowed in the current mode (Initiator/Target) are
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* asserted.
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*/
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#define SCSISIGO 0x003
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#define CDO 0x80
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#define IOO 0x40
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#define MSGO 0x20
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#define ATNO 0x10
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#define SELO 0x08
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#define BSYO 0x04
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#define REQO 0x02
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#define ACKO 0x01
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/*
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* SCSI Rate Control (p. 3-17).
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* Contents of this register determine the Synchronous SCSI data transfer
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* rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
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* SOFS (3:0) bits disables synchronous data transfers. Any offset value
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* greater than 0 enables synchronous transfers.
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*/
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#define SCSIRATE 0x004
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#define WIDEXFER 0x80 /* Wide transfer control */
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#define SXFR 0x70 /* Sync transfer rate */
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#define SOFS 0x0f /* Sync offset */
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/*
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* SCSI ID (p. 3-18).
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* Contains the ID of the board and the current target on the
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* selected channel
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*/
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#define SCSIID 0x005
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#define TID 0xf0 /* Target ID mask */
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#define OID 0x0f /* Our ID mask */
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/*
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* SCSI Transfer Count (pp. 3-19,20)
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* These registers count down the number of bytes transfered
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* across the SCSI bus. The counter is decremented only once
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* the data has been safely transfered. SDONE in SSTAT0 is
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* set when STCNT goes to 0
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*/
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#define STCNT 0x008
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/*
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* SCSI Status 0 (p. 3-21)
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* Contains one set of SCSI Interrupt codes
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* These are most likely of interest to the sequencer
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*/
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#define SSTAT0 0x00b
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#define TARGET 0x80 /* Board is a target */
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#define SELDO 0x40 /* Selection Done */
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#define SELDI 0x20 /* Board has been selected */
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#define SELINGO 0x10 /* Selection In Progress */
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#define SWRAP 0x08 /* 24bit counter wrap */
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#define SDONE 0x04 /* STCNT = 0x000000 */
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#define SPIORDY 0x02 /* SCSI PIO Ready */
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#define DMADONE 0x01 /* DMA transfer completed */
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/*
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* Clear SCSI Interrupt 1 (p. 3-23)
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* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
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*/
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#define CLRSINT1 0x00c
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#define CLRSELTIMEO 0x80
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#define CLRATNO 0x40
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#define CLRSCSIRSTI 0x20
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/* UNUSED 0x10 */
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#define CLRBUSFREE 0x08
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#define CLRSCSIPERR 0x04
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#define CLRPHASECHG 0x02
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#define CLRREQINIT 0x01
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/*
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* SCSI Status 1 (p. 3-24)
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* These interrupt bits are of interest to the kernel driver
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*/
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#define SSTAT1 0x00c
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#define SELTO 0x80
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#define ATNTARG 0x40
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#define SCSIRSTI 0x20
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#define PHASEMIS 0x10
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#define BUSFREE 0x08
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#define SCSIPERR 0x04
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#define PHASECHG 0x02
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#define REQINIT 0x01
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/*
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* SCSI/Host Address (p. 3-30)
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* These registers hold the host address for the byte about to be
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* transfered on the SCSI bus. They are counted up in the same
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* manner as STCNT is counted down. SHADDR should always be used
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* to determine the address of the last byte transfered since HADDR
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* can be squewed by write ahead.
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*/
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#define SHADDR 0x014
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/*
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* Selection/Reselection ID (p. 3-31)
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* Upper four bits are the device id. The ONEBIT is set when the re/selecting
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* device did not set its own ID.
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*/
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#define SELID 0x019
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#define SELID_MASK 0xf0
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#define ONEBIT 0x08
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/* UNUSED 0x07 */
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/*
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* SCSI Block Control (p. 3-32)
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* Controls Bus type and channel selection. In a twin channel configuration
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* addresses 0x00-0x1e are gated to the appropriate channel based on this
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* register. SELWIDE allows for the coexistence of 8bit and 16bit devices
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* on a wide bus.
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*/
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#define SBLKCTL 0x01f
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/* UNUSED 0xc0 */
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#define AUTOFLUSHDIS 0x20
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/* UNUSED 0x10 */
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#define SELBUSB 0x08
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/* UNUSED 0x04 */
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#define SELWIDE 0x02
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/* UNUSED 0x01 */
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/*
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* Sequencer Control (p. 3-33)
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* Error detection mode and speed configuration
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*/
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#define SEQCTL 0x060
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#define PERRORDIS 0x80
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#define PAUSEDIS 0x40
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#define FAILDIS 0x20
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#define FASTMODE 0x10
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#define BRKADRINTEN 0x08
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#define STEP 0x04
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#define SEQRESET 0x02
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#define LOADRAM 0x01
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/*
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* Sequencer RAM Data (p. 3-34)
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* Single byte window into the Scratch Ram area starting at the address
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* specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
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* four bytes in sucessesion. The SEQADDRs will increment after the most
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* significant byte is written
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*/
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#define SEQRAM 0x061
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/*
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* Sequencer Address Registers (p. 3-35)
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* Only the first bit of SEQADDR1 holds addressing information
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*/
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#define SEQADDR0 0x062
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#define SEQADDR1 0x063
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#define SEQADDR1_MASK 0x01
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/*
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* Accumulator
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* We cheat by passing arguments in the Accumulator up to the kernel driver
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*/
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#define ACCUM 0x064
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#define SINDEX 0x065
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/*
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* Board Control (p. 3-43)
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*/
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#define BCTL 0x084
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/* RSVD 0xf0 */
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#define ACE 0x08 /* Support for external processors */
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/* RSVD 0x06 */
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#define ENABLE 0x01
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/*
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* Bus On/Off Time (p. 3-44)
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*/
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#define BUSTIME 0x085
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#define BOFF 0xf0
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#define BON 0x0f
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/*
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* Bus Speed (p. 3-45)
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*/
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#define BUSSPD 0x086
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#define DFTHRSH 0xc0
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#define STBOFF 0x38
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#define STBON 0x07
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/*
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* Host Control (p. 3-47) R/W
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* Overal host control of the device.
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*/
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#define HCNTRL 0x087
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/* UNUSED 0x80 */
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#define POWRDN 0x40
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/* UNUSED 0x20 */
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#define SWINT 0x10
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#define IRQMS 0x08
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#define PAUSE 0x04
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#define INTEN 0x02
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#define CHIPRST 0x01
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/*
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* Host Address (p. 3-48)
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* This register contains the address of the byte about
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* to be transfered across the host bus.
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*/
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#define HADDR 0x088
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/*
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* SCB Pointer (p. 3-49)
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* Gate one of the four SCBs into the SCBARRAY window.
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*/
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#define SCBPTR 0x090
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/*
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* Interrupt Status (p. 3-50)
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* Status for system interrupts
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*/
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#define INTSTAT 0x091
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#define SEQINT_MASK 0xf0 /* SEQINT Status Codes */
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#define BAD_PHASE 0x00
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#define SEND_REJECT 0x10
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#define NO_IDENT 0x20
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#define NO_MATCH 0x30
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#define MSG_SDTR 0x40
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#define MSG_WDTR 0x50
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#define MSG_REJECT 0x60
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#define BAD_STATUS 0x70
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#define RESIDUAL 0x80
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#define ABORT_TAG 0x90
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#define AWAITING_MSG 0xa0
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#define IMMEDDONE 0xb0
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#define BRKADRINT 0x08
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#define SCSIINT 0x04
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#define CMDCMPLT 0x02
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#define SEQINT 0x01
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#define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
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/*
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* Hard Error (p. 3-53)
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* Reporting of catastrophic errors. You usually cannot recover from
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* these without a full board reset.
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*/
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#define ERROR 0x092
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/* UNUSED 0xf0 */
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#define PARERR 0x08
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#define ILLOPCODE 0x04
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#define ILLSADDR 0x02
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#define ILLHADDR 0x01
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/*
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* Clear Interrupt Status (p. 3-52)
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*/
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#define CLRINT 0x092
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#define CLRBRKADRINT 0x08
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#define CLRSCSIINT 0x04
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#define CLRCMDINT 0x02
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#define CLRSEQINT 0x01
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/*
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* SCB Auto Increment (p. 3-59)
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* Byte offset into the SCB Array and an optional bit to allow auto
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* incrementing of the address during download and upload operations
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*/
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#define SCBCNT 0x09a
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#define SCBAUTO 0x80
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#define SCBCNT_MASK 0x1f
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/*
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* Queue In FIFO (p. 3-60)
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* Input queue for queued SCBs (commands that the seqencer has yet to start)
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*/
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#define QINFIFO 0x09b
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/*
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* Queue In Count (p. 3-60)
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* Number of queued SCBs
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*/
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#define QINCNT 0x09c
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/*
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* Queue Out FIFO (p. 3-61)
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* Queue of SCBs that have completed and await the host
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*/
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#define QOUTFIFO 0x09d
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/*
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* Queue Out Count (p. 3-61)
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* Number of queued SCBs in the Out FIFO
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*/
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#define QOUTCNT 0x09e
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#define SCBARRAY 0x0a0
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/* --------------------- AIC-7870-only definitions -------------------- */
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#define DSPCISTATUS 0x086
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/*
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* Serial EEPROM Control (p. 4-92 in 7870 Databook)
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* Controls the reading and writing of an external serial 1-bit
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* EEPROM Device. In order to access the serial EEPROM, you must
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* first set the SEEMS bit that generates a request to the memory
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* port for access to the serial EEPROM device. When the memory
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* port is not busy servicing another request, it reconfigures
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* to allow access to the serial EEPROM. When this happens, SEERDY
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* gets set high to verify that the memory port access has been
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* granted.
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*
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* After successful arbitration for the memory port, the SEECS bit of
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* the SEECTL register is connected to the chip select. The SEECK,
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* SEEDO, and SEEDI are connected to the clock, data out, and data in
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* lines respectively. The SEERDY bit of SEECTL is useful in that it
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* gives us an 800 nsec timer. After a write to the SEECTL register,
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* the SEERDY goes high 800 nsec later. The one exception to this is
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* when we first request access to the memory port. The SEERDY goes
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* high to signify that access has been granted and, for this case, has
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* no implied timing.
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*
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* See 93cx6.c for detailed information on the protocol necessary to
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* read the serial EEPROM.
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*/
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#define SEECTL 0x01e
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#define EXTARBACK 0x80
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#define EXTARBREQ 0x40
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#define SEEMS 0x20
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#define SEERDY 0x10
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#define SEECS 0x08
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#define SEECK 0x04
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#define SEEDO 0x02
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#define SEEDI 0x01
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/* ---------------------- Scratch RAM Offsets ------------------------- */
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/* These offsets are either to values that are initialized by the board's
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* BIOS or are specified by the Linux sequencer code. If I can figure out
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* how to read the EISA configuration info at probe time, the cards could
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* be run without BIOS support installed
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*/
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/*
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* 1 byte per target starting at this address for configuration values
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*/
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#define HA_TARG_SCRATCH 0x020
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/*
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* The sequencer will stick the frist byte of any rejected message here so
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* we can see what is getting thrown away.
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*/
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#define HA_REJBYTE 0x031
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/*
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* Bit vector of targets that have disconnection disabled.
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*/
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#define HA_DISC_DSB 0x032
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/*
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* Length of pending message
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*/
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#define HA_MSG_LEN 0x034
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/*
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* message body
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*/
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#define HA_MSG_START 0x035 /* outgoing message body */
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/*
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* These are offsets into the card's scratch ram. Some of the values are
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* specified in the AHA2742 technical reference manual and are initialized
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* by the BIOS at boot time.
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*/
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#define HA_ARG_1 0x04a
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#define HA_RETURN_1 0x04a
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#define SEND_SENSE 0x80
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#define SEND_WDTR 0x80
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#define SEND_SDTR 0x80
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#define SEND_REJ 0x40
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#define SG_COUNT 0x04d
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#define SG_NEXT 0x04e
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#define HA_SIGSTATE 0x04b
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#define HA_SCBCOUNT 0x052
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#define HA_FLAGS 0x053
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#define SINGLE_BUS 0x00
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#define TWIN_BUS 0x01
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#define WIDE_BUS 0x02
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#define ACTIVE_MSG 0x20
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#define IDENTIFY_SEEN 0x40
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#define RESELECTING 0x80
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#define HA_ACTIVE0 0x054
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#define HA_ACTIVE1 0x055
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#define SAVED_TCL 0x056
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#define WAITING_SCBH 0x057
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#define WAITING_SCBT 0x058
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#define HA_SCSICONF 0x05a
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#define HA_HOSTCONF 0x05d
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#define HA_274_BIOSCTRL 0x05f
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#define BIOSMODE 0x30
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#define BIOSDISABLED 0x30
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#define MSG_ABORT 0x06
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#define MSG_BUS_DEVICE_RESET 0x0c
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#define BUS_8_BIT 0x00
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#define BUS_16_BIT 0x01
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#define BUS_32_BIT 0x02
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