0351824ff8
- Make power a uint8_t rather than a uint16_t. - Replace the hardcoded RF chains. Reviewed by: avos
602 lines
17 KiB
C
602 lines
17 KiB
C
/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/if_rtwn_ridx.h>
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#include <dev/rtwn/if_rtwn_rx.h>
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#include <dev/rtwn/rtl8812a/r12a.h>
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#include <dev/rtwn/rtl8812a/r12a_reg.h>
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#include <dev/rtwn/rtl8812a/r12a_var.h>
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static void
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r12a_write_txpower(struct rtwn_softc *sc, int chain,
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struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
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{
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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/* Write per-CCK rate Tx power. */
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rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain),
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SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) |
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SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) |
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SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) |
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SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11]));
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}
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/* Write per-OFDM rate Tx power. */
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rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain),
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SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) |
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SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) |
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SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) |
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SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18]));
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rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain),
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SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) |
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SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) |
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SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) |
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SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54]));
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/* Write per-MCS Tx power. */
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rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain),
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SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_MCS(0)]) |
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SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_MCS(1)]) |
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SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_MCS(2)]) |
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SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_MCS(3)]));
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rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain),
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SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_MCS(4)]) |
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SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_MCS(5)]) |
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SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_MCS(6)]) |
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SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_MCS(7)]));
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if (sc->ntxchains >= 2) {
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rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain),
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SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_MCS(8)]) |
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SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_MCS(9)]) |
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SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_MCS(10)]) |
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SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_MCS(11)]));
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rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain),
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SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_MCS(12)]) |
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SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_MCS(13)]) |
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SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_MCS(14)]) |
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SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_MCS(15)]));
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}
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/* TODO: VHT rates */
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}
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static int
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r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t chan;
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int group;
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chan = rtwn_chan2centieee(c);
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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if (chan <= 2) group = 0;
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else if (chan <= 5) group = 1;
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else if (chan <= 8) group = 2;
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else if (chan <= 11) group = 3;
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else if (chan <= 14) group = 4;
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else {
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KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
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return (-1);
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}
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} else if (IEEE80211_IS_CHAN_5GHZ(c)) {
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if (chan < 36)
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return (-1);
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if (chan <= 42) group = 0;
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else if (chan <= 48) group = 1;
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else if (chan <= 58) group = 2;
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else if (chan <= 64) group = 3;
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else if (chan <= 106) group = 4;
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else if (chan <= 114) group = 5;
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else if (chan <= 122) group = 6;
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else if (chan <= 130) group = 7;
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else if (chan <= 138) group = 8;
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else if (chan <= 144) group = 9;
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else if (chan <= 155) group = 10;
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else if (chan <= 161) group = 11;
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else if (chan <= 171) group = 12;
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else if (chan <= 177) group = 13;
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else {
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KASSERT(0, ("wrong 5GHz channel %d!\n", chan));
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return (-1);
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}
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} else {
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KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
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return (-1);
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}
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return (group);
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}
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static void
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r12a_get_txpower(struct rtwn_softc *sc, int chain,
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struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
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{
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struct r12a_softc *rs = sc->sc_priv;
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int i, ridx, group, max_mcs;
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/* Determine channel group. */
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group = r12a_get_power_group(sc, c);
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if (group == -1) { /* shouldn't happen */
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device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
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return;
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}
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/* TODO: VHT rates. */
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max_mcs = RTWN_RIDX_MCS(sc->ntxchains * 8 - 1);
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/* XXX regulatory */
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/* XXX net80211 regulatory */
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
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power[ridx] = rs->cck_tx_pwr[chain][group];
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for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
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power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
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for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
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power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
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for (i = 0; i < sc->ntxchains; i++) {
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uint8_t min_mcs;
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uint8_t pwr_diff;
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#ifdef notyet
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if (IEEE80211_IS_CHAN_HT80(c)) {
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/* Vendor driver uses HT40 values here. */
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pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
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} else
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#endif
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if (IEEE80211_IS_CHAN_HT40(c))
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pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
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else
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pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
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min_mcs = RTWN_RIDX_MCS(i * 8);
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for (ridx = min_mcs; ridx <= max_mcs; ridx++)
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power[ridx] += pwr_diff;
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}
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} else { /* 5GHz */
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for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
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power[ridx] = rs->ht40_tx_pwr_5g[chain][group];
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for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
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power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0];
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for (i = 0; i < sc->ntxchains; i++) {
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uint8_t min_mcs;
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uint8_t pwr_diff;
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#ifdef notyet
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if (IEEE80211_IS_CHAN_HT80(c)) {
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/* TODO: calculate base value. */
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pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i];
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} else
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#endif
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if (IEEE80211_IS_CHAN_HT40(c))
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pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i];
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else
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pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i];
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min_mcs = RTWN_RIDX_MCS(i * 8);
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for (ridx = min_mcs; ridx <= max_mcs; ridx++)
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power[ridx] += pwr_diff;
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}
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}
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/* Apply max limit. */
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for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
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if (power[ridx] > R92C_MAX_TX_PWR)
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power[ridx] = R92C_MAX_TX_PWR;
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}
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#ifdef RTWN_DEBUG
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if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
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/* Dump per-rate Tx power values. */
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printf("Tx power for chain %d:\n", chain);
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for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++)
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printf("Rate %d = %u\n", ridx, power[ridx]);
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}
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#endif
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}
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static void
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r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t power[RTWN_RIDX_COUNT];
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int i;
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for (i = 0; i < sc->ntxchains; i++) {
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memset(power, 0, sizeof(power));
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/* Compute per-rate Tx power values. */
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r12a_get_txpower(sc, i, c, power);
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/* Write per-rate Tx power values to hardware. */
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r12a_write_txpower(sc, i, c, power);
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}
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}
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void
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r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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struct r12a_softc *rs = sc->sc_priv;
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uint16_t chan = rtwn_chan2centieee(c);
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if (rs->chip & R12A_CHIP_C_CUT) {
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if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) {
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rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);
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rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
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} else {
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rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);
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if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */
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(chan == 13 || chan == 14)) {
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rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
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rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
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0, 0x40000000);
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} else { /* !80 Mhz */
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rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
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rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
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0x40000000, 0);
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}
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}
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} else {
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/* Set ADC clock to 160M to resolve 2480 MHz spur. */
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if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */
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(chan == 13 || chan == 14))
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rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
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else if (IEEE80211_IS_CHAN_2GHZ(c))
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rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
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}
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}
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static void
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r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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struct ieee80211com *ic = &sc->sc_ic;
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struct r12a_softc *rs = sc->sc_priv;
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uint32_t basicrates;
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uint8_t swing;
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int i;
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/* Check if band was changed. */
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if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) !=
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RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^
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!(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ))
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return;
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rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates,
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NULL, 1);
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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rtwn_r12a_set_band_2ghz(sc, basicrates);
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swing = rs->tx_bbswing_2g;
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} else if (IEEE80211_IS_CHAN_5GHZ(c)) {
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rtwn_r12a_set_band_5ghz(sc, basicrates);
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swing = rs->tx_bbswing_5g;
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} else {
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KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags));
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return;
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}
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/* XXX PATH_B is set by vendor driver. */
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for (i = 0; i < 2; i++) {
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uint16_t val = 0;
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switch ((swing >> i * 2) & 0x3) {
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case 0:
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val = 0x200; /* 0 dB */
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break;
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case 1:
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val = 0x16a; /* -3 dB */
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break;
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case 2:
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val = 0x101; /* -6 dB */
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break;
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case 3:
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val = 0xb6; /* -9 dB */
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break;
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}
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rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M,
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val << R12A_TX_SCALE_SWING_S);
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}
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}
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void
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r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint32_t val;
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uint16_t chan;
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int i;
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r12a_set_band(sc, c);
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chan = rtwn_chan2centieee(c);
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if (36 <= chan && chan <= 48)
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val = 0x09280000;
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else if (50 <= chan && chan <= 64)
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val = 0x08a60000;
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else if (100 <= chan && chan <= 116)
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val = 0x08a40000;
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else if (118 <= chan)
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val = 0x08240000;
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else
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val = 0x12d40000;
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rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);
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for (i = 0; i < sc->nrxchains; i++) {
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if (36 <= chan && chan <= 64)
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val = 0x10100;
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else if (100 <= chan && chan <= 140)
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val = 0x30100;
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else if (140 < chan)
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val = 0x50100;
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else
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val = 0x00000;
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rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val);
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/* RTL8812AU-specific */
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rtwn_r12a_fix_spur(sc, c);
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KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan));
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rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan);
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}
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#ifdef notyet
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if (IEEE80211_IS_CHAN_HT80(c)) { /* 80 MHz */
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rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x80, 0x100);
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/* TODO */
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val = 0x0;
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} else
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#endif
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if (IEEE80211_IS_CHAN_HT40(c)) { /* 40 MHz */
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uint8_t ext_chan;
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if (IEEE80211_IS_CHAN_HT40U(c))
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ext_chan = R12A_DATA_SEC_PRIM_DOWN_20;
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else
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ext_chan = R12A_DATA_SEC_PRIM_UP_20;
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rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
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rtwn_write_1(sc, R12A_DATA_SEC, ext_chan);
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rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);
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rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
|
|
|
|
/* discard high 4 bits */
|
|
val = rtwn_bb_read(sc, R12A_RFMOD);
|
|
val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan);
|
|
rtwn_bb_write(sc, R12A_RFMOD, val);
|
|
|
|
val = rtwn_bb_read(sc, R12A_CCA_ON_SEC);
|
|
val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan);
|
|
rtwn_bb_write(sc, R12A_CCA_ON_SEC, val);
|
|
|
|
if (rtwn_read_1(sc, 0x837) & 0x04)
|
|
val = 0x01800000;
|
|
else if (sc->nrxchains == 2 && sc->ntxchains == 2)
|
|
val = 0x01c00000;
|
|
else
|
|
val = 0x02000000;
|
|
|
|
rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
|
|
|
|
if (IEEE80211_IS_CHAN_HT40U(c))
|
|
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);
|
|
else
|
|
rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);
|
|
|
|
val = 0x400;
|
|
} else { /* 20 MHz */
|
|
rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
|
|
rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
|
|
|
|
rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);
|
|
rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
|
|
|
|
if (sc->nrxchains == 2 && sc->ntxchains == 2)
|
|
val = 0x01c00000;
|
|
else
|
|
val = 0x02000000;
|
|
|
|
rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
|
|
|
|
val = 0xc00;
|
|
}
|
|
|
|
/* RTL8812AU-specific */
|
|
rtwn_r12a_fix_spur(sc, c);
|
|
|
|
for (i = 0; i < sc->nrxchains; i++)
|
|
rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val);
|
|
|
|
/* Set Tx power for this new channel. */
|
|
r12a_set_txpower(sc, c);
|
|
}
|
|
|
|
void
|
|
r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates)
|
|
{
|
|
struct r12a_softc *rs = sc->sc_priv;
|
|
|
|
/* Enable CCK / OFDM. */
|
|
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN,
|
|
0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM);
|
|
|
|
rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);
|
|
rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);
|
|
|
|
/* Select AGC table. */
|
|
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);
|
|
|
|
switch (rs->rfe_type) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
|
|
break;
|
|
case 3:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
|
|
break;
|
|
case 4:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);
|
|
break;
|
|
case 5:
|
|
rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
|
|
rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
|
|
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
|
|
|
|
/* Write basic rates. */
|
|
rtwn_set_basicrates(sc, basicrates);
|
|
|
|
rtwn_write_1(sc, R12A_CCK_CHECK, 0);
|
|
}
|
|
|
|
void
|
|
r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates)
|
|
{
|
|
struct r12a_softc *rs = sc->sc_priv;
|
|
int ntries;
|
|
|
|
rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ);
|
|
|
|
for (ntries = 0; ntries < 100; ntries++) {
|
|
if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)
|
|
break;
|
|
|
|
rtwn_delay(sc, 25);
|
|
}
|
|
if (ntries == 100) {
|
|
device_printf(sc->sc_dev,
|
|
"%s: TXPKT_EMPTY check failed (%04X)\n",
|
|
__func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY));
|
|
}
|
|
|
|
/* Enable OFDM. */
|
|
rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK,
|
|
R12A_OFDMCCK_EN_OFDM);
|
|
|
|
rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);
|
|
rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);
|
|
|
|
/* Select AGC table. */
|
|
rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);
|
|
|
|
switch (rs->rfe_type) {
|
|
case 0:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
|
|
break;
|
|
case 1:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
|
|
break;
|
|
case 2:
|
|
case 4:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
|
|
break;
|
|
case 3:
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
|
|
rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
|
|
break;
|
|
case 5:
|
|
rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33);
|
|
rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
|
|
rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);
|
|
rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
|
|
rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);
|
|
|
|
/* Write basic rates. */
|
|
rtwn_set_basicrates(sc, basicrates);
|
|
}
|