189 lines
4.7 KiB
C
189 lines
4.7 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __XLP_HAL_UART_H__
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#define __XLP_HAL_UART_H__
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/* UART Specific registers */
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#define UART_RX_DATA 0x00
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#define UART_TX_DATA 0x00
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#define UART_INT_EN 0x01
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#define UART_INT_ID 0x02
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#define UART_FIFO_CTL 0x02
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#define UART_LINE_CTL 0x03
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#define UART_MODEM_CTL 0x04
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#define UART_LINE_STS 0x05
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#define UART_MODEM_STS 0x06
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#define UART_DIVISOR0 0x00
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#define UART_DIVISOR1 0x01
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#define BASE_BAUD (XLP_IO_CLK/16)
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#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
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/* LCR mask values */
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#define LCR_5BITS 0x00
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#define LCR_6BITS 0x01
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#define LCR_7BITS 0x02
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#define LCR_8BITS 0x03
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#define LCR_STOPB 0x04
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#define LCR_PENAB 0x08
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#define LCR_PODD 0x00
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#define LCR_PEVEN 0x10
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#define LCR_PONE 0x20
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#define LCR_PZERO 0x30
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#define LCR_SBREAK 0x40
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#define LCR_EFR_ENABLE 0xbf
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#define LCR_DLAB 0x80
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/* MCR mask values */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DRS 0x04
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#define MCR_IE 0x08
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#define MCR_LOOPBACK 0x10
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/* FCR mask values */
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#define FCR_RCV_RST 0x02
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#define FCR_XMT_RST 0x04
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#define FCR_RX_LOW 0x00
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#define FCR_RX_MEDL 0x40
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#define FCR_RX_MEDH 0x80
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#define FCR_RX_HIGH 0xc0
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/* IER mask values */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_uart_pcibase(node, inst) \
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nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
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#define nlm_get_uart_regbase(node, inst) \
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(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
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static inline void
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nlm_uart_set_baudrate(uint64_t base, int baud)
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{
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uint32_t lcr;
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lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
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/* enable divisor register, and write baud values */
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nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
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nlm_write_uart_reg(base, UART_DIVISOR0,
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(BAUD_DIVISOR(baud) & 0xff));
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nlm_write_uart_reg(base, UART_DIVISOR1,
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((BAUD_DIVISOR(baud) >> 8) & 0xff));
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/* restore default lcr */
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nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
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}
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static inline void
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nlm_uart_outbyte(uint64_t base, char c)
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{
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uint32_t lsr;
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for (;;) {
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lsr = nlm_read_uart_reg(base, UART_LINE_STS);
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if (lsr & 0x20)
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break;
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}
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nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
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}
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static inline char
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nlm_uart_inbyte(uint64_t base)
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{
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int data, lsr;
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for (;;) {
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lsr = nlm_read_uart_reg(base, UART_LINE_STS);
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if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
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data = 0;
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break;
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}
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if (lsr & 0x01) { /* Rx data */
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data = nlm_read_uart_reg(base, UART_RX_DATA);
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break;
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}
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}
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return (char)data;
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}
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static inline int
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nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
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int parity, int int_en, int loopback)
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{
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uint32_t lcr;
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lcr = 0;
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if (databits >= 8)
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lcr |= LCR_8BITS;
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else if (databits == 7)
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lcr |= LCR_7BITS;
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else if (databits == 6)
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lcr |= LCR_6BITS;
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else
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lcr |= LCR_5BITS;
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if (stopbits > 1)
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lcr |= LCR_STOPB;
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lcr |= parity << 3;
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/* setup default lcr */
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nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
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/* Reset the FIFOs */
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nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
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nlm_uart_set_baudrate(base, baud);
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if (loopback)
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nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
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if (int_en)
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nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
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return 0;
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}
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#endif /* !LOCORE && !__ASSEMBLY__ */
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#endif /* __XLP_HAL_UART_H__ */
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