2fe18afefc
or unsigned int (this doesn't change the struct layout, size or alignment in any of the files changed in this commit, at least for gcc on i386's. Using bitfields of type u_char may affect size and alignment but not packing)).
348 lines
9.7 KiB
C
348 lines
9.7 KiB
C
/*
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.12 1998/03/03 14:19:09 dg Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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#define FXP_DEVICEID_i82557 0x1229
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#define FXP_PCI_MMBA 0x10
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#define FXP_PCI_IOBA 0x14
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/*
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* Control/status registers.
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*/
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#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
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#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
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#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
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#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
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#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
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#define FXP_CSR_PORT 8 /* port (4 bytes) */
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#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
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#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
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#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
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/*
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* FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
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*
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* volatile u_int8_t :2,
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* scb_rus:4,
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* scb_cus:2;
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*/
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#define FXP_PORT_SOFTWARE_RESET 0
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#define FXP_PORT_SELFTEST 1
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#define FXP_PORT_SELECTIVE_RESET 2
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#define FXP_PORT_DUMP 3
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#define FXP_SCB_RUS_IDLE 0
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#define FXP_SCB_RUS_SUSPENDED 1
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#define FXP_SCB_RUS_NORESOURCES 2
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#define FXP_SCB_RUS_READY 4
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#define FXP_SCB_RUS_SUSP_NORBDS 9
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#define FXP_SCB_RUS_NORES_NORBDS 10
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#define FXP_SCB_RUS_READY_NORBDS 12
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#define FXP_SCB_CUS_IDLE 0
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#define FXP_SCB_CUS_SUSPENDED 1
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#define FXP_SCB_CUS_ACTIVE 2
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#define FXP_SCB_STATACK_SWI 0x04
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#define FXP_SCB_STATACK_MDI 0x08
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#define FXP_SCB_STATACK_RNR 0x10
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#define FXP_SCB_STATACK_CNA 0x20
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#define FXP_SCB_STATACK_FR 0x40
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#define FXP_SCB_STATACK_CXTNO 0x80
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#define FXP_SCB_COMMAND_CU_NOP 0x00
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#define FXP_SCB_COMMAND_CU_START 0x10
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#define FXP_SCB_COMMAND_CU_RESUME 0x20
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#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
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#define FXP_SCB_COMMAND_CU_DUMP 0x50
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#define FXP_SCB_COMMAND_CU_BASE 0x60
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#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
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#define FXP_SCB_COMMAND_RU_NOP 0
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#define FXP_SCB_COMMAND_RU_START 1
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#define FXP_SCB_COMMAND_RU_RESUME 2
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#define FXP_SCB_COMMAND_RU_ABORT 4
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#define FXP_SCB_COMMAND_RU_LOADHDS 5
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#define FXP_SCB_COMMAND_RU_BASE 6
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#define FXP_SCB_COMMAND_RU_RBDRESUME 7
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/*
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* Command block definitions
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*/
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struct fxp_cb_nop {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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};
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struct fxp_cb_ias {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int8_t macaddr[6];
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};
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/* I hate bit-fields :-( */
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struct fxp_cb_config {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int byte_count:6,
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:2;
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volatile u_int rx_fifo_limit:4,
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tx_fifo_limit:3,
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:1;
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volatile u_int8_t adaptive_ifs;
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volatile u_int :8;
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volatile u_int rx_dma_bytecount:7,
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:1;
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volatile u_int tx_dma_bytecount:7,
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dma_bce:1;
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volatile u_int late_scb:1,
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:1,
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tno_int:1,
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ci_int:1,
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:3,
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save_bf:1;
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volatile u_int disc_short_rx:1,
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underrun_retry:2,
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:5;
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volatile u_int mediatype:1,
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:7;
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volatile u_int :8;
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volatile u_int :3,
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nsai:1,
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preamble_length:2,
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loopback:2;
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volatile u_int linear_priority:3,
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:5;
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volatile u_int linear_pri_mode:1,
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:3,
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interfrm_spacing:4;
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volatile u_int :8;
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volatile u_int :8;
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volatile u_int promiscuous:1,
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bcast_disable:1,
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:5,
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crscdt:1;
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volatile u_int :8;
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volatile u_int :8;
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volatile u_int stripping:1,
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padding:1,
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rcv_crc_xfer:1,
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:5;
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volatile u_int :6,
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force_fdx:1,
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fdx_pin_en:1;
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volatile u_int :6,
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multi_ia:1,
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:1;
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volatile u_int :3,
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mc_all:1,
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:4;
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};
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#define MAXMCADDR 80
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struct fxp_cb_mcs {
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struct fxp_cb_tx *next;
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struct mbuf *mb_head;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int16_t mc_cnt;
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volatile u_int8_t mc_addr[MAXMCADDR][6];
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};
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/*
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* Number of DMA segments in a TxCB. Note that this is carefully
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* chosen to make the total struct size an even power of two. It's
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* critical that no TxCB be split across a page boundry since
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* no attempt is made to allocate physically contiguous memory.
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*
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*/
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#ifdef __alpha__ /* XXX - should be conditional on pointer size */
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#define FXP_NTXSEG 28
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#else
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#define FXP_NTXSEG 29
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#endif
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struct fxp_tbd {
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volatile u_int32_t tb_addr;
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volatile u_int32_t tb_size;
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};
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struct fxp_cb_tx {
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struct fxp_cb_tx *next;
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struct mbuf *mb_head;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int32_t tbd_array_addr;
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volatile u_int16_t byte_count;
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volatile u_int8_t tx_threshold;
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volatile u_int8_t tbd_number;
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/*
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* The following isn't actually part of the TxCB.
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*/
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volatile struct fxp_tbd tbd[FXP_NTXSEG];
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};
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/*
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* Control Block (CB) definitions
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*/
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/* status */
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#define FXP_CB_STATUS_OK 0x2000
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#define FXP_CB_STATUS_C 0x8000
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/* commands */
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#define FXP_CB_COMMAND_NOP 0x0
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#define FXP_CB_COMMAND_IAS 0x1
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#define FXP_CB_COMMAND_CONFIG 0x2
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#define FXP_CB_COMMAND_MCAS 0x3
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#define FXP_CB_COMMAND_XMIT 0x4
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#define FXP_CB_COMMAND_RESRV 0x5
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#define FXP_CB_COMMAND_DUMP 0x6
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#define FXP_CB_COMMAND_DIAG 0x7
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/* command flags */
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#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
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#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
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#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
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#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
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/*
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* RFA definitions
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*/
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struct fxp_rfa {
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volatile u_int16_t rfa_status;
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volatile u_int16_t rfa_control;
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volatile u_int32_t link_addr;
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volatile u_int32_t rbd_addr;
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volatile u_int16_t actual_size;
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volatile u_int16_t size;
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};
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#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
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#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
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#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
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#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
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#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
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#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
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#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
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#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
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#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
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#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
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#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
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#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
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#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
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#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
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#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
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/*
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* Statistics dump area definitions
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*/
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struct fxp_stats {
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volatile u_int32_t tx_good;
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volatile u_int32_t tx_maxcols;
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volatile u_int32_t tx_latecols;
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volatile u_int32_t tx_underruns;
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volatile u_int32_t tx_lostcrs;
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volatile u_int32_t tx_deffered;
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volatile u_int32_t tx_single_collisions;
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volatile u_int32_t tx_multiple_collisions;
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volatile u_int32_t tx_total_collisions;
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volatile u_int32_t rx_good;
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volatile u_int32_t rx_crc_errors;
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volatile u_int32_t rx_alignment_errors;
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volatile u_int32_t rx_rnr_errors;
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volatile u_int32_t rx_overrun_errors;
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volatile u_int32_t rx_cdt_errors;
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volatile u_int32_t rx_shortframes;
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volatile u_int32_t completion_status;
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};
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#define FXP_STATS_DUMP_COMPLETE 0xa005
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#define FXP_STATS_DR_COMPLETE 0xa007
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/*
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* Serial EEPROM control register bits
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*/
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/* shift clock */
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#define FXP_EEPROM_EESK 0x01
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/* chip select */
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#define FXP_EEPROM_EECS 0x02
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/* data in */
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#define FXP_EEPROM_EEDI 0x04
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/* data out */
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#define FXP_EEPROM_EEDO 0x08
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/*
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* Serial EEPROM opcodes, including start bit
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*/
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#define FXP_EEPROM_OPC_ERASE 0x4
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#define FXP_EEPROM_OPC_WRITE 0x5
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#define FXP_EEPROM_OPC_READ 0x6
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/*
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* Management Data Interface opcodes
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*/
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#define FXP_MDI_WRITE 0x1
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#define FXP_MDI_READ 0x2
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/*
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* PHY device types
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*/
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#define FXP_PHY_NONE 0
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#define FXP_PHY_82553A 1
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#define FXP_PHY_82553C 2
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#define FXP_PHY_82503 3
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_82555 7
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#define FXP_PHY_DP83840A 10
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#define FXP_PHY_82555B 11
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/*
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* PHY BMCR Basic Mode Control Register
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*/
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
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#define FXP_PHY_BMCR_AUTOEN 0x1000
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#define FXP_PHY_BMCR_SPEED_100M 0x2000
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/*
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* DP84830 PHY, PCS Configuration Register
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*/
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#define FXP_DP83840_PCR 0x17
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#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */
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#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */
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#define FXP_DP83840_PCR_BIT8 0x0100
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#define FXP_DP83840_PCR_BIT10 0x0400
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