252 lines
8.6 KiB
C
252 lines
8.6 KiB
C
/* tc-i386.h -- Header file for tc-i386.c
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Copyright (C) 1989, 1992 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/*
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* $Id$
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*/
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#ifndef TC_I386
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#define TC_I386 1
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#define AOUT_MACHTYPE 134
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#define REVERSE_SORT_RELOCS
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#define LOCAL_LABELS_FB
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#define tc_coff_symbol_emit_hook(a) ; /* not used */
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/* Local labels starts with .L */
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/* fixme-now: this is for testing against old gas */
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/* #define LOCAL_LABEL(name) ((name)[0] == '.' && (name)[1] == 'L') */
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#define tc_aout_pre_write_hook(x) {;} /* not used */
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#define tc_crawl_symbol_chain(a) {;} /* not used */
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#define tc_headers_hook(a) {;} /* not used */
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#define MAX_OPERANDS 3 /* max operands per insn */
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#define MAX_PREFIXES 4 /* max prefixes per opcode */
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#define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */
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#define MAX_MEMORY_OPERANDS 2 /* max memory ref per insn
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* lcall uses 2
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*/
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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#define PREFIX_SEPERATOR '/'
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#ifndef OLD_GAS
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#define NOP_OPCODE 0x90
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#else /* OLD_GAS */
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#define NOP_OPCODE 0x00
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#endif /* OLD_GAS */
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/* register numbers */
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#define EBP_REG_NUM 5
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#define ESP_REG_NUM 4
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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/* these are the att as opcode suffixes, making movl --> mov, for example */
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#define DWORD_OPCODE_SUFFIX 'l'
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#define WORD_OPCODE_SUFFIX 'w'
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#define BYTE_OPCODE_SUFFIX 'b'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3 /* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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#define END_OF_INSN '\0'
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/*
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When an operand is read in it is classified by its type. This type includes
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all the possible ways an operand can be used. Thus, '%eax' is both 'register
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# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
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'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
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Operands are classified so that we can match given operand types with
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the opcode table in i386-opcode.h.
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*/
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#define Unknown 0x0
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
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#define WordReg (Reg16|Reg32) /* for push/pop operands */
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/* immediate */
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#define Imm8 0x8 /* 8 bit immediate */
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#define Imm8S 0x10 /* 8 bit immediate sign extended */
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#define Imm16 0x20 /* 16 bit immediate */
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#define Imm32 0x40 /* 32 bit immediate */
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#define Imm1 0x80 /* 1 bit immediate */
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#define ImmUnknown Imm32 /* for unknown expressions */
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#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
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/* memory */
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#define Disp8 0x200 /* 8 bit displacement (for jumps) */
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#define Disp16 0x400 /* 16 bit displacement */
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#define Disp32 0x800 /* 32 bit displacement */
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#define Disp (Disp8|Disp16|Disp32) /* General displacement */
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#define DispUnknown Disp32 /* for unknown size displacements */
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#define Mem8 0x1000
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#define Mem16 0x2000
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#define Mem32 0x4000
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#define BaseIndex 0x8000
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#define Mem (Disp|Mem8|Mem16|Mem32|BaseIndex) /* General memory */
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#define WordMem (Mem16|Mem32|Disp|BaseIndex)
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#define ByteMem (Mem8|Disp|BaseIndex)
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/* specials */
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#define InOutPortReg 0x10000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x20000 /* register to hold shift cound = cl */
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#define Control 0x40000 /* Control register */
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#define Debug 0x80000 /* Debug register */
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#define Test 0x100000 /* Test register */
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#define FloatReg 0x200000 /* Float register */
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#define FloatAcc 0x400000 /* Float stack top %st(0) */
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#define SReg2 0x800000 /* 2 bit segment register */
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#define SReg3 0x1000000 /* 3 bit segment register */
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#define Acc 0x2000000 /* Accumulator %al or %ax or %eax */
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define JumpAbsolute 0x4000000
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#define Abs8 0x08000000
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#define Abs16 0x10000000
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#define Abs32 0x20000000
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#define Abs (Abs8|Abs16|Abs32)
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#define Byte (Reg8|Imm8|Imm8S)
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#define Word (Reg16|Imm16)
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#define DWord (Reg32|Imm32)
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#define SMALLEST_DISP_TYPE(num) \
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fits_in_signed_byte(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32)
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typedef struct {
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte with a optional prefix(es). */
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unsigned int base_opcode;
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/* extension_opcode is the 3 bit extension for group <n> insns.
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If this template has no extension opcode (the usual case) use None */
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unsigned char extension_opcode;
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#define None 0xff /* If no extension_opcode is possible. */
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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the same instruction */
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define W 0x1 /* set if operands are words or dwords */
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#define D 0x2 /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
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/* direction flag for floating insns: MUST BE 0x400 */
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#define FloatD 0x400
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/* shorthand */
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#define DW (D|W)
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */
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#define Seg2ShortForm 0x40 /* encoding of load segment reg insns */
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#define Seg3ShortForm 0x80 /* fs/gs segment register insns. */
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#define Jump 0x100 /* special case for jump insns. */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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/* 0x400 CANNOT BE USED since it's already used by FloatD above */
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#define DONT_USE 0x400
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#define NoModrm 0x800
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#define Modrm 0x1000
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#define imulKludge 0x2000
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#define JumpByte 0x4000
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#define JumpDword 0x8000
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#define ReverseRegRegmem 0x10000
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/* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
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instuction comes in byte, word, and dword sizes and is encoded into
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machine code in the canonical way. */
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#define COMES_IN_ALL_SIZES (W)
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/* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
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source and destination operands can be reversed by setting either
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the D (for integer insns) or the FloatD (for floating insns) bit
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in base_opcode. */
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#define COMES_IN_BOTH_DIRECTIONS (D|FloatD)
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/* operand_types[i] describes the type of operand i. This is made
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by OR'ing together all of the possible type masks. (e.g.
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'operand_types[i] = Reg|Imm' specifies that operand i can be
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either a register or an immediate operand */
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unsigned int operand_types[3];
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} template;
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/*
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'templates' is for grouping together 'template' structures for opcodes
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of the same name. This is only used for storing the insns in the grand
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ole hash table of insns.
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The templates themselves start at START and range up to (but not including)
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END.
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*/
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typedef struct {
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template *start;
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template *end;
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} templates;
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/* these are for register name --> number & type hash lookup */
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typedef struct {
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char *reg_name;
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unsigned int reg_type;
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unsigned int reg_num;
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} reg_entry;
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typedef struct {
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char *seg_name;
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unsigned int seg_prefix;
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} seg_entry;
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/* these are for prefix name --> prefix code hash lookup */
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typedef struct {
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char *prefix_name;
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unsigned char prefix_code;
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} prefix_entry;
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/* 386 operand encoding bytes: see 386 book for details of this. */
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typedef struct {
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unsigned regmem:3; /* codes register or memory operand */
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unsigned reg:3; /* codes register operand (or extended opcode) */
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unsigned mode:2; /* how to interpret regmem & reg */
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} modrm_byte;
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/* 386 opcode byte to code indirect addressing. */
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typedef struct {
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unsigned base:3;
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unsigned index:3;
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unsigned scale:2;
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} base_index_byte;
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#endif /* TC_I386 */
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/* end of tc-i386.h */
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