e34a491b35
These clock nodes are used by the IPQ4018/IPQ4019 and derivatives. They're also used by other 32 and 64 bit qualcomm parts; so it's best to put these nodes here in a single qcom_clk driver and add to it as we grow new Qualcomm SoC support. Tested: * IPQ4018, boot Differential Revision: https://reviews.freebsd.org/D33665
291 lines
7.5 KiB
C
291 lines
7.5 KiB
C
/*-
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include "qcom_clk_branch2.h"
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#include "qcom_clk_branch2_reg.h"
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#include "clkdev_if.h"
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/*
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* This is a combination gate/status and dynamic hardware clock gating with
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* voting.
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*/
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#if 0
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#define DPRINTF(dev, msg...) device_printf(dev, msg);
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#else
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#define DPRINTF(dev, msg...)
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#endif
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struct qcom_clk_branch2_sc {
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struct clknode *clknode;
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uint32_t flags;
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uint32_t enable_offset;
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uint32_t enable_shift;
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uint32_t hwcg_reg;
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uint32_t hwcg_bit;
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uint32_t halt_reg;
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uint32_t halt_check_type;
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bool halt_check_voted;
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};
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#if 0
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static bool
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qcom_clk_branch2_get_gate_locked(struct qcom_clk_branch2_sc *sc)
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{
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uint32_t reg;
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
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®);
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: offset=0x%x, reg=0x%x\n", __func__,
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sc->enable_offset, reg);
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return (!! (reg & (1U << sc->enable_shift)));
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}
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#endif
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static int
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qcom_clk_branch2_init(struct clknode *clk, device_t dev)
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{
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static bool
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qcom_clk_branch2_in_hwcg_mode_locked(struct qcom_clk_branch2_sc *sc)
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{
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uint32_t reg;
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if (sc->hwcg_reg == 0)
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return (false);
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->hwcg_reg,
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®);
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return (!! (reg & (1U << sc->hwcg_bit)));
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}
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static bool
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qcom_clk_branch2_check_halt_locked(struct qcom_clk_branch2_sc *sc, bool enable)
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{
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uint32_t reg;
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->halt_reg, ®);
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if (enable) {
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/*
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* The upstream Linux code is .. unfortunate.
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*
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* Here it says "return true if BRANCH_CLK_OFF is not set,
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* or if the status field = FSM_STATUS_ON AND
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* the clk_off field is 0.
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*
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* Which .. is weird, because I can't currently see
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* how we'd ever need to check FSM_STATUS_ON - the only
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* valid check for the FSM status also requires clk_off=0.
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*/
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return !! ((reg & QCOM_CLK_BRANCH2_CLK_OFF) == 0);
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} else {
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return !! (reg & QCOM_CLK_BRANCH2_CLK_OFF);
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}
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}
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/*
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* Check if the given type/voted flag match what is configured.
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*/
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static bool
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qcom_clk_branch2_halt_check_type(struct qcom_clk_branch2_sc *sc,
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uint32_t type, bool voted)
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{
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return ((sc->halt_check_type == type) &&
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(sc->halt_check_voted == voted));
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}
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static bool
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qcom_clk_branch2_wait_locked(struct qcom_clk_branch2_sc *sc, bool enable)
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{
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if (qcom_clk_branch2_halt_check_type(sc,
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QCOM_CLK_BRANCH2_BRANCH_HALT_SKIP, false))
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return (true);
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if (qcom_clk_branch2_in_hwcg_mode_locked(sc))
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return (true);
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if ((qcom_clk_branch2_halt_check_type(sc,
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QCOM_CLK_BRANCH2_BRANCH_HALT_DELAY, false)) ||
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(enable == false && sc->halt_check_voted)) {
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DELAY(10);
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return (true);
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}
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if ((qcom_clk_branch2_halt_check_type(sc,
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QCOM_CLK_BRANCH2_BRANCH_HALT_INVERTED, false)) ||
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(qcom_clk_branch2_halt_check_type(sc,
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QCOM_CLK_BRANCH2_BRANCH_HALT, false)) ||
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(enable && sc->halt_check_voted)) {
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int count;
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for (count = 0; count < 200; count++) {
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if (qcom_clk_branch2_check_halt_locked(sc, enable))
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return (true);
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DELAY(1);
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}
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: enable stuck (%d)!\n", __func__, enable);
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return (false);
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}
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/* Default */
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return (true);
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}
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static int
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qcom_clk_branch2_set_gate(struct clknode *clk, bool enable)
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{
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struct qcom_clk_branch2_sc *sc;
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uint32_t reg;
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sc = clknode_get_softc(clk);
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DPRINTF(clknode_get_device(sc->clknode), "%s: called\n", __func__);
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if (sc->enable_offset == 0) {
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: no enable_offset", __func__);
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return (ENXIO);
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}
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: called; enable=%d\n", __func__, enable);
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CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
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CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
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®);
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if (enable) {
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reg |= (1U << sc->enable_shift);
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} else {
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reg &= ~(1U << sc->enable_shift);
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}
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CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->enable_offset,
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reg);
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/*
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* Now wait for the clock branch to update!
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*/
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if (! qcom_clk_branch2_wait_locked(sc, enable)) {
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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DPRINTF(clknode_get_device(sc->clknode),
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"%s: failed to wait!\n", __func__);
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return (ENXIO);
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}
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
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return (0);
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}
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static int
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qcom_clk_branch2_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
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int flags, int *stop)
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{
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struct qcom_clk_branch2_sc *sc;
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sc = clknode_get_softc(clk);
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/* We only support what our parent clock is currently set as */
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*fout = fin;
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/* .. and stop here if we don't have SET_RATE_PARENT */
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if (sc->flags & QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT)
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*stop = 0;
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else
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*stop = 1;
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return (0);
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}
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static clknode_method_t qcom_clk_branch2_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, qcom_clk_branch2_init),
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CLKNODEMETHOD(clknode_set_gate, qcom_clk_branch2_set_gate),
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CLKNODEMETHOD(clknode_set_freq, qcom_clk_branch2_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(qcom_clk_branch2, qcom_clk_branch2_class,
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qcom_clk_branch2_methods, sizeof(struct qcom_clk_branch2_sc),
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clknode_class);
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int
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qcom_clk_branch2_register(struct clkdom *clkdom,
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struct qcom_clk_branch2_def *clkdef)
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{
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struct clknode *clk;
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struct qcom_clk_branch2_sc *sc;
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if (clkdef->flags & QCOM_CLK_BRANCH2_FLAGS_CRITICAL)
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clkdef->clkdef.flags |= CLK_NODE_CANNOT_STOP;
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clk = clknode_create(clkdom, &qcom_clk_branch2_class,
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&clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->clknode = clk;
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sc->enable_offset = clkdef->enable_offset;
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sc->enable_shift = clkdef->enable_shift;
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sc->halt_reg = clkdef->halt_reg;
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sc->hwcg_reg = clkdef->hwcg_reg;
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sc->hwcg_bit = clkdef->hwcg_bit;
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sc->halt_check_type = clkdef->halt_check_type;
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sc->halt_check_voted = clkdef->halt_check_voted;
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sc->flags = clkdef->flags;
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clknode_register(clkdom, clk);
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return (0);
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}
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