afa8862328
a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
105 lines
4.7 KiB
C
105 lines
4.7 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
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* $FreeBSD$
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*/
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/*
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*
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* Register definitions for the Intel 8253 Programmable Interval Timer.
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*
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* This chip has three independent 16-bit down counters that can be
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* read on the fly. There are three mode registers and three countdown
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* registers. The countdown registers are addressed directly, via the
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* first three I/O ports. The three mode registers are accessed via
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* the fourth I/O port, with two bits in the mode byte indicating the
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* register. (Why are hardware interfaces always so braindead?).
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*
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* To write a value into the countdown register, the mode register
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* is first programmed with a command indicating the which byte of
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* the two byte register is to be modified. The three possibilities
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* are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
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* msb (TMR_MR_BOTH).
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*
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* To read the current value ("on the fly") from the countdown register,
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* you write a "latch" command into the mode register, then read the stable
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* value from the corresponding I/O port. For example, you write
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* TMR_MR_LATCH into the corresponding mode register. Presumably,
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* after doing this, a write operation to the I/O port would result
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* in undefined behavior (but hopefully not fry the chip).
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* Reading in this manner has no side effects.
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*
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* [IBM-PC]
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* The outputs of the three timers are connected as follows:
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*
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* timer 0 -> irq 0
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* timer 1 -> dma chan 0 (for dram refresh)
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* timer 2 -> speaker (via keyboard controller)
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*
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* Timer 0 is used to call hardclock.
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* Timer 2 is used to generate console beeps.
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*
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* [PC-9801]
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* The outputs of the three timers are connected as follows:
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*
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* timer 0 -> irq 0
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* timer 1 -> speaker (via keyboard controller)
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* timer 2 -> RS232C
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*
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* Timer 0 is used to call hardclock.
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* Timer 1 is used to generate console beeps.
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*/
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/*
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* Macros for specifying values to be written into a mode register.
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*/
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#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
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#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
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#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
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#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
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#define TIMER_SEL0 0x00 /* select counter 0 */
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#define TIMER_SEL1 0x40 /* select counter 1 */
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#define TIMER_SEL2 0x80 /* select counter 2 */
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#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
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#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
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#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
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#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
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#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
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#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
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#define TIMER_LATCH 0x00 /* latch counter for reading */
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#define TIMER_LSB 0x10 /* r/w counter LSB */
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#define TIMER_MSB 0x20 /* r/w counter MSB */
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#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
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#define TIMER_BCD 0x01 /* count in BCD */
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