7c12b677f5
These are older MIPS4kc parts from Atheros. They typically ran at sub-200MHz and have 11bg, 11a, or 11abg wifi MAC/PHYs integrated. This port is the initial non-wifi pieces required to bring up the chip. I'll commit the redboot and other pieces later, and then hopefully(!) wifi support will follow. Submitted by: Mori Hiroki <yamori813@yahoo.co.jp> Differential Revision: https://reviews.freebsd.org/D7237
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef __AR5315_CPUDEF_H__
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#define __AR5315_CPUDEF_H__
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struct ar5315_cpu_def {
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void (* detect_mem_size) (void);
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void (* detect_sys_frequency) (void);
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void (* ar5315_chip_device_reset) (void);
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void (* ar5315_chip_device_start) (void);
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int (* ar5315_chip_device_stopped) (uint32_t);
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void (* ar5315_chip_set_pll_ge) (int, int);
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void (* ar5315_chip_set_mii_speed) (uint32_t, uint32_t);
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void (* ar5315_chip_ddr_flush_ge) (int);
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uint32_t (* ar5315_chip_get_eth_pll) (unsigned int, int);
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void (* ar5315_chip_soc_init) (void);
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/*
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* Allow to change MII bus mode:
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* AR5315_ARGE_MII_MODE_MII
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* AR5315_ARGE_MII_MODE_RMII
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* AR5315_ARGE_MII_MODE_GMII
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* AR5315_ARGE_MII_MODE_RGMII
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* mii_mode(unit, mode);
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*/
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#define AR5315_ARGE_MII_MODE_MII 0x0100
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#define AR5315_ARGE_MII_MODE_RMII 0x0101
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#define AR5315_ARGE_MII_MODE_GMII 0x1000
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#define AR5315_ARGE_MII_MODE_RGMII 0x1001
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void (* ar5315_chip_set_mii_mode) (int, int, int);
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};
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extern struct ar5315_cpu_def * ar5315_cpu_ops;
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static inline void ar531x_detect_mem_size(void)
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{
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ar5315_cpu_ops->detect_mem_size();
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}
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static inline void ar531x_detect_sys_frequency(void)
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{
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ar5315_cpu_ops->detect_sys_frequency();
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}
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static inline void ar531x_device_reset(void)
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{
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ar5315_cpu_ops->ar5315_chip_device_reset();
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}
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static inline void ar531x_device_start(void)
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{
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ar5315_cpu_ops->ar5315_chip_device_start();
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}
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static inline int ar531x_device_stopped(uint32_t mask)
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{
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return ar5315_cpu_ops->ar5315_chip_device_stopped(mask);
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}
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static inline void ar531x_device_set_pll_ge(int unit, int speed)
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{
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ar5315_cpu_ops->ar5315_chip_set_pll_ge(unit, speed);
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}
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static inline void ar531x_device_set_mii_speed(int unit, int speed)
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{
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ar5315_cpu_ops->ar5315_chip_set_mii_speed(unit, speed);
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}
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static inline void ar531x_device_flush_ddr_ge(int unit)
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{
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ar5315_cpu_ops->ar5315_chip_ddr_flush_ge(unit);
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}
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static inline void ar531x_device_soc_init(void)
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{
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ar5315_cpu_ops->ar5315_chip_soc_init();
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}
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static inline void ar531x_device_set_mii_mode(int unit, int mode, int speed)
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{
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ar5315_cpu_ops->ar5315_chip_set_mii_mode(unit, mode, speed);
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}
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/* XXX shouldn't be here! */
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extern uint32_t u_ar531x_cpu_freq;
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extern uint32_t u_ar531x_ahb_freq;
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extern uint32_t u_ar531x_ddr_freq;
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extern uint32_t u_ar531x_uart_addr;
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extern uint32_t u_ar531x_gpio_di;
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extern uint32_t u_ar531x_gpio_do;
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extern uint32_t u_ar531x_gpio_cr;
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extern uint32_t u_ar531x_gpio_pins;
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extern uint32_t u_ar531x_wdog_ctl;
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extern uint32_t u_ar531x_wdog_timer;
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static inline uint32_t ar531x_cpu_freq(void) { return u_ar531x_cpu_freq; }
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static inline uint32_t ar531x_ahb_freq(void) { return u_ar531x_ahb_freq; }
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static inline uint32_t ar531x_ddr_freq(void) { return u_ar531x_ddr_freq; }
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static inline uint32_t ar531x_uart_addr(void) { return u_ar531x_uart_addr; }
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static inline uint32_t ar531x_gpio_di(void) { return u_ar531x_gpio_di; }
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static inline uint32_t ar531x_gpio_cr(void) { return u_ar531x_gpio_cr; }
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static inline uint32_t ar531x_gpio_do(void) { return u_ar531x_gpio_do; }
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static inline uint32_t ar531x_gpio_pins(void) { return u_ar531x_gpio_pins; }
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static inline uint32_t ar531x_wdog_ctl(void) { return u_ar531x_wdog_ctl; }
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static inline uint32_t ar531x_wdog_timer(void) { return u_ar531x_wdog_timer; }
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#endif
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