530 lines
12 KiB
ArmAsm
530 lines
12 KiB
ArmAsm
/*-
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* Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.s"
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#include <machine/asm.h>
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#include <machine/param.h>
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#include <machine/spr.h>
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#include <machine/psl.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/tlb.h>
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#include <machine/bootinfo.h>
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#define TMPSTACKSZ 16384
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.text
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.globl btext
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btext:
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.globl kernel_text
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kernel_text:
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/*
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* Startup entry. Note, this must be the first thing in the text segment!
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*/
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.text
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.globl __start
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__start:
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/*
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* Assumptions on the boot loader:
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* - system memory starts from physical address 0
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* - it's mapped by a single TBL1 entry
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* - TLB1 mapping is 1:1 pa to va
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* - kernel is loaded at 16MB boundary
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* - all PID registers are set to the same value
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* - CPU is running in AS=0
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*
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* Registers contents provided by the loader(8):
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* r1 : stack pointer
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* r3 : metadata pointer
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*
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* We rearrange the TLB1 layout as follows:
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* - find TLB1 entry we started in
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* - make sure it's protected, ivalidate other entries
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* - create temp entry in the second AS (make sure it's not TLB[1])
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* - switch to temp mapping
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* - map 16MB of RAM in TLB1[1]
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* - use AS=1, set EPN to KERNBASE and RPN to kernel load address
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* - switch to to TLB1[1] mapping
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* - invalidate temp mapping
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*
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* locore registers use:
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* r1 : stack pointer
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* r2 : trace pointer (AP only, for early diagnostics)
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* r3-r27 : scratch registers
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* r28 : kernload
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* r29 : temp TLB1 entry
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* r30 : initial TLB1 entry we started in
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* r31 : metadata pointer
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*/
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/*
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* Keep metadata ptr in r31 for later use.
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*/
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mr %r31, %r3
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/*
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* Initial cleanup
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*/
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li %r3, PSL_DE /* Keep debug exceptions for CodeWarrior. */
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mtmsr %r3
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isync
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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/*
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* Locate the TLB1 entry that maps this code
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*/
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bl 1f
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1: mflr %r3
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bl tlb1_find_current /* the entry number found is returned in r30 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary mapping in AS=1 and switch to it
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*/
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bl tlb1_temp_mapping_as1
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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bl 2f
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2: mflr %r4
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addi %r4, %r4, 20
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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mr %r3, %r30
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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/* Final kernel mapping, map in 16 MB of RAM */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r4, 1 /* Entry 1 */
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rlwimi %r3, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r3
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isync
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li %r3, (TLB_SIZE_16M << MAS1_TSIZE_SHIFT)@l
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oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
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isync
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lis %r3, KERNBASE@h
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ori %r3, %r3, KERNBASE@l /* EPN = KERNBASE */
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mtspr SPR_MAS2, %r3
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isync
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/* Discover phys load address */
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bl 3f
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3: mflr %r4 /* Use current address */
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rlwinm %r4, %r4, 0, 0, 7 /* 16MB alignment mask */
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mr %r28, %r4 /* Keep kernel load address */
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ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r4 /* Set RPN and protection */
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isync
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tlbwe
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isync
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msync
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/* Switch to the above TLB1[1] mapping */
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bl 4f
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4: mflr %r4
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rlwinm %r4, %r4, 0, 8, 31 /* Current offset from kernel load address */
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rlwinm %r3, %r3, 0, 0, 19
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add %r4, %r4, %r3 /* Convert to kernel virtual address */
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addi %r4, %r4, 36
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li %r3, PSL_DE /* Note AS=0 */
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi
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/*
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* Invalidate temp mapping
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*/
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mr %r3, %r29
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bl tlb1_inval_entry
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/*
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* Save kernel load address for later use.
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*/
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lis %r3, kernload@ha
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addi %r3, %r3, kernload@l
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stw %r28, 0(%r3)
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/*
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* Setup a temporary stack
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*/
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lis %r1, tmpstack@ha
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addi %r1, %r1, tmpstack@l
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addi %r1, %r1, (TMPSTACKSZ - 8)
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/*
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* Initialise exception vector offsets
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*/
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bl ivor_setup
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/*
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* Set up arguments and jump to system initialization code
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*/
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lis %r3, kernel_text@ha
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addi %r3, %r3, kernel_text@l
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lis %r4, _end@ha
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addi %r4, %r4, _end@l
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mr %r5, %r31 /* metadata ptr */
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/* Prepare e500 core */
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bl e500_init
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/* Switch to thread0.td_kstack now */
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mr %r1, %r3
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li %r3, 0
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stw %r3, 0(%r1)
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/* Machine independet part, does not return */
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bl mi_startup
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/* NOT REACHED */
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5: b 5b
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/*
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* Invalidate all entries in the given TLB.
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*
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* r3 TLBSEL
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*/
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tlb_inval_all:
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rlwinm %r3, %r3, 3, 0x18 /* TLBSEL */
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ori %r3, %r3, 0x4 /* INVALL */
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tlbivax 0, %r3
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isync
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msync
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tlbsync
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msync
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blr
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/*
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* expects address to look up in r3, returns entry number in r30
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*
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* FIXME: the hidden assumption is we are now running in AS=0, but we should
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* retrieve actual AS from MSR[IS|DS] and put it in MAS6[SAS]
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*/
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tlb1_find_current:
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mfspr %r17, SPR_PID0
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slwi %r17, %r17, MAS6_SPID0_SHIFT
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mtspr SPR_MAS6, %r17
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isync
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tlbsx 0, %r3
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mfspr %r17, SPR_MAS0
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rlwinm %r30, %r17, 16, 20, 31 /* MAS0[ESEL] -> r30 */
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/* Make sure we have IPROT set on the entry */
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mfspr %r17, SPR_MAS1
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oris %r17, %r17, MAS1_IPROT@h
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mtspr SPR_MAS1, %r17
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Invalidates a single entry in TLB1.
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*
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* r3 ESEL
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* r4-r5 scratched
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*/
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tlb1_inval_entry:
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lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r4, %r3, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r4
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isync
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tlbre
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li %r5, 0 /* MAS1[V] = 0 */
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* r30 current entry number
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* r29 returned temp entry
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* r3-r5 scratched
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*/
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tlb1_temp_mapping_as1:
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/* Read our current translation */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r3, %r30, 16, 12, 15 /* Select our current entry */
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mtspr SPR_MAS0, %r3
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isync
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tlbre
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/*
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* Prepare and write temp entry
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*
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* FIXME this is not robust against overflow i.e. when the current
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* entry is the last in TLB1
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*/
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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addi %r29, %r30, 1 /* Use next entry. */
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li %r4, 1
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cmpw %r4, %r29
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bne 1f
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addi %r29, %r29, 1
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1: rlwimi %r3, %r29, 16, 12, 15 /* Select temp entry */
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mtspr SPR_MAS0, %r3
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isync
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mfspr %r5, SPR_MAS1
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li %r4, 1 /* AS=1 */
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rlwimi %r5, %r4, 12, 19, 19
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li %r4, 0 /* Global mapping, TID=0 */
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rlwimi %r5, %r4, 16, 8, 15
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oris %r5, %r5, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Loops over TLB1, invalidates all entries skipping the one which currently
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* maps this code.
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*
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* r30 current entry
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* r3-r5 scratched
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*/
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tlb1_inval_all_but_current:
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mr %r6, %r3
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mfspr %r3, SPR_TLB1CFG /* Get number of entries */
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andi. %r3, %r3, TLBCFG_NENTRY_MASK@l
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li %r4, 0 /* Start from Entry 0 */
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1: lis %r5, MAS0_TLBSEL1@h
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rlwimi %r5, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r5
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isync
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tlbre
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mfspr %r5, SPR_MAS1
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cmpw %r4, %r30 /* our current entry? */
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beq 2f
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rlwinm %r5, %r5, 0, 2, 31 /* clear VALID and IPROT bits */
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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2: addi %r4, %r4, 1
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cmpw %r4, %r3 /* Check if this is the last entry */
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bne 1b
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blr
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/************************************************************************/
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/* locore subroutines */
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/************************************************************************/
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ivor_setup:
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/* Set base address of interrupt handler routines */
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lis %r3, interrupt_vector_base@h
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mtspr SPR_IVPR, %r3
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/* Assign interrupt handler routines offsets */
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li %r3, int_critical_input@l
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mtspr SPR_IVOR0, %r3
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li %r3, int_machine_check@l
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mtspr SPR_IVOR1, %r3
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li %r3, int_data_storage@l
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mtspr SPR_IVOR2, %r3
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li %r3, int_instr_storage@l
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mtspr SPR_IVOR3, %r3
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li %r3, int_external_input@l
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mtspr SPR_IVOR4, %r3
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li %r3, int_alignment@l
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mtspr SPR_IVOR5, %r3
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li %r3, int_program@l
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mtspr SPR_IVOR6, %r3
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li %r3, int_syscall@l
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mtspr SPR_IVOR8, %r3
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li %r3, int_decrementer@l
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mtspr SPR_IVOR10, %r3
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li %r3, int_fixed_interval_timer@l
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mtspr SPR_IVOR11, %r3
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li %r3, int_watchdog@l
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mtspr SPR_IVOR12, %r3
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li %r3, int_data_tlb_error@l
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mtspr SPR_IVOR13, %r3
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li %r3, int_inst_tlb_error@l
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mtspr SPR_IVOR14, %r3
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li %r3, int_debug@l
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mtspr SPR_IVOR15, %r3
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blr
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/*
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* Cache disable/enable/inval sequences according
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* to section 2.16 of E500CORE RM.
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*/
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ENTRY(dcache_inval)
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/* Invalidate d-cache */
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mfspr %r3, SPR_L1CSR0
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ori %r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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1: mfspr %r3, SPR_L1CSR0
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andi. %r3, %r3, L1CSR0_DCFI
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bne 1b
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blr
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ENTRY(dcache_disable)
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/* Disable d-cache */
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mfspr %r3, SPR_L1CSR0
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li %r4, L1CSR0_DCE@l
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not %r4, %r4
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and %r3, %r3, %r4
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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blr
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ENTRY(dcache_enable)
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/* Enable d-cache */
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mfspr %r3, SPR_L1CSR0
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oris %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h
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ori %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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blr
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ENTRY(icache_inval)
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/* Invalidate i-cache */
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mfspr %r3, SPR_L1CSR1
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ori %r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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1: mfspr %r3, SPR_L1CSR1
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andi. %r3, %r3, L1CSR1_ICFI
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bne 1b
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blr
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ENTRY(icache_disable)
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/* Disable i-cache */
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mfspr %r3, SPR_L1CSR1
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li %r4, L1CSR1_ICE@l
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not %r4, %r4
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and %r3, %r3, %r4
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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blr
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ENTRY(icache_enable)
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/* Enable i-cache */
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mfspr %r3, SPR_L1CSR1
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oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h
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ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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blr
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/*
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* int setfault()
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*
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* Similar to setjmp to setup for handling faults on accesses to user memory.
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* Any routine using this may only call bcopy, either the form below,
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* or the (currently used) C code optimized, so it doesn't use any non-volatile
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* registers.
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*/
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.globl setfault
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setfault:
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mflr %r0
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mfsprg0 %r4
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lwz %r4, PC_CURTHREAD(%r4)
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lwz %r4, TD_PCB(%r4)
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stw %r3, PCB_ONFAULT(%r4)
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mfcr %r10
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mfctr %r11
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mfxer %r12
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stw %r0, 0(%r3)
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stw %r1, 4(%r3)
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stw %r2, 8(%r3)
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stmw %r10, 12(%r3) /* store CR, CTR, XER, [r13 .. r31] */
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li %r3, 0 /* return FALSE */
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blr
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/************************************************************************/
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/* Data section */
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/************************************************************************/
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.data
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.align 4
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tmpstack:
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.space TMPSTACKSZ
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/*
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* Compiled KERNBASE locations
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*/
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.globl kernbase
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.set kernbase, KERNBASE
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/*
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* Globals
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*/
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#define INTRCNT_COUNT 256 /* max(HROWPIC_IRQMAX,OPENPIC_IRQMAX) */
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GLOBAL(kernload)
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.long 0
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GLOBAL(intrnames)
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.space INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
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GLOBAL(eintrnames)
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.align 4
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GLOBAL(intrcnt)
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.space INTRCNT_COUNT * 4 * 2
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GLOBAL(eintrcnt)
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#include <powerpc/booke/trap_subr.S>
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