694c651803
sn(4) driver and also looking at newer drivers. The reason for the rewrite is to support MII and to try and resolve some performance issues found when trying to use the sn(4) driver on the Gumstix network boards. For reference, the SMSC LAN91C111 is a non-PCI ethernet part whose lineage dates back to Ye Olde Days of ISA. It seems to get some use in the embedded space these days on parts lacking on-board MACs or on-board PCI controllers, such as the XScale PXA line of ARM CPUs. This also includes a driver for the SMSC LAN83C183 10/100 PHY. Man page to follow.
262 lines
10 KiB
C
262 lines
10 KiB
C
/*-
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* Copyright (c) 2006 Benno Rice. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _IF_SMCREG_H_
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#define _IF_SMCREG_H_
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/* All Banks, Offset 0xe: Bank Select Register */
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#define BSR 0xe
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#define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */
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#define BSR_IDENTIFY 0x3300 /* Static value for identification */
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#define BSR_IDENTIFY_MASK 0xff00
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/* Bank 0, Offset 0x0: Transmit Control Register */
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#define TCR 0x0
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#define TCR_TXENA 0x0001 /* Enable/disable transmitter */
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#define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */
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#define TCR_FORCOL 0x0004 /* Force a collision */
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#define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
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#define TCR_NOCRC 0x0100 /* Disable/enable CRC */
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#define TCR_MON_CSN 0x0400 /* Monitor carrier signal */
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#define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */
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#define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */
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#define TCR_EPH_LOOP 0x2000 /* Internal loopback */
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#define TCR_SWFDUP 0x8000 /* Switched full duplex */
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/* Bank 0, Offset 0x2: EPH Status Register */
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#define EPHSR 0x2
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#define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
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#define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */
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#define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */
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#define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */
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#define EPHSR_16COL 0x0010 /* 16 collisions on last TX */
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#define EPHSR_SQET 0x0020 /* Signal quality error test */
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#define EPHSR_LTX_BRD 0x0040 /* Last TX was broadcast */
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#define EPHSR_TX_DEFR 0x0080 /* Transmit deferred */
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#define EPHSR_LATCOL 0x0200 /* Late collision on last TX */
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#define EPHSR_LOST_CARR 0x0400 /* Lost carrier sense */
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#define EPHSR_EXC_DEF 0x0800 /* Excessive deferral */
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#define EPHSR_CTR_ROL 0x1000 /* Counter rollover */
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#define EPHSR_LINK_OK 0x4000 /* Inverse of nLNK pin */
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#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */
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/* Bank 0, Offset 0x4: Receive Control Register */
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#define RCR 0x4
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#define RCR_RX_ABORT 0x0001 /* RX aborted */
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#define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */
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#define RCR_ALMUL 0x0004 /* Accept all multicast frames */
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#define RCR_RXEN 0x0100 /* Enable/disable receiver */
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#define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
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#define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */
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#define RCR_FILT_CAR 0x4000 /* Filter leading 12 bits of carrier */
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#define RCR_SOFT_RST 0x8000 /* Software reset */
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/* Bank 0, Offset 0x6: Counter Register */
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#define ECR 0x6
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#define ECR_SNGLCOL_MASK 0x000f /* Single collisions */
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#define ECR_SNGLCOL_SHIFT 0
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#define ECR_MULCOL_MASK 0x00f0 /* Multiple collisions */
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#define ECR_MULCOL_SHIFT 4
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#define ECR_TX_DEFR_MASK 0x0f00 /* Transmit deferrals */
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#define ECR_TX_DEFR_SHIFT 8
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#define ECR_EXC_DEF_MASK 0xf000 /* Excessive deferrals */
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#define ECR_EXC_DEF_SHIFT 12
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/* Bank 0, Offset 0x8: Memory Information Register */
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#define MIR 0x8
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#define MIR_SIZE_MASK 0x00ff /* Memory size (2k pages) */
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#define MIR_SIZE_SHIFT 0
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#define MIR_FREE_MASK 0xff00 /* Memory free (2k pages) */
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#define MIR_FREE_SHIFT 8
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#define MIR_PAGE_SIZE 2048
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/* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
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#define RPCR 0xa
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#define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */
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#define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
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#define RPCR_SPEED 0x2000 /* Manual speed selection */
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#define RPCR_LSA_MASK 0x00e0 /* Select LED A function */
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#define RPCR_LSA_SHIFT 5
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#define RPCR_LSB_MASK 0x001c /* Select LED B function */
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#define RPCR_LSB_SHIFT 2
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#define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */
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#define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */
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#define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */
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#define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */
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#define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
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#define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
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#define RPCR_LED_ACT_TX 0x7 /* TX activity detected */
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/* Bank 1, Offset 0x0: Configuration Register */
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#define CR 0x0
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#define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */
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#define CR_GPCNTRL 0x0400 /* Inverse drives nCNTRL pin */
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#define CR_NO_WAIT 0x1000 /* Do not request additional waits */
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#define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
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/* Bank 1, Offset 0x2: Base Address Register */
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#define BAR 0x2
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#define BAR_HIGH_MASK 0xe000
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#define BAR_LOW_MASK 0x1f00
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#define BAR_LOW_SHIFT 4
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#define BAR_ADDRESS(val) \
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((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT))
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/* Bank 1, Offsets 0x4: Individual Address Registers */
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#define IAR0 0x4
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#define IAR1 0x5
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#define IAR2 0x6
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#define IAR3 0x7
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#define IAR4 0x8
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#define IAR5 0x9
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/* Bank 1, Offset 0xa: General Purpose Register */
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#define GPR 0xa
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/* Bank 1, Offset 0xc: Control Register */
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#define CTR 0xa
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#define CTR_STORE 0x0001 /* Store registers to EEPROM */
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#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */
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#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
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#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
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#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
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#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
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#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
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#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
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/* Bank 2, Offset 0x0: MMU Command Register */
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#define MMUCR 0x0
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#define MMUCR_BUSY 0x0001 /* MMU is busy */
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#define MMUCR_CMD_NOOP (0<<5) /* No operation */
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#define MMUCR_CMD_TX_ALLOC (1<<5) /* Alloc TX memory (256b chunks) */
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#define MMUCR_CMD_MMU_RESET (2<<5) /* Reset MMU */
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#define MMUCR_CMD_REMOVE (3<<5) /* Remove frame from RX FIFO */
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#define MMUCR_CMD_RELEASE (4<<5) /* Remove and release from RX FIFO */
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#define MMUCR_CMD_RELEASE_PKT (5<<5) /* Release packet specified in PNR */
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#define MMUCR_CMD_ENQUEUE (6<<5) /* Enqueue packet for TX */
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#define MMUCR_CMD_TX_RESET (7<<5) /* Reset TX FIFOs */
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/* Bank 2, Offset 0x2: Packet Number Register */
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#define PNR 0x2
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#define PNR_MASK 0x3fff
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/* Bank 2, Offset 0x3: Allocation Result Register */
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#define ARR 0x3
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#define ARR_FAILED 0x8000 /* Last allocation request failed */
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#define ARR_MASK 0x3000
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/* Bank 2, Offset 0x4: FIFO Ports Register */
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#define FIFO_TX 0x4
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#define FIFO_RX 0x5
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#define FIFO_EMPTY 0x80 /* FIFO empty */
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#define FIFO_PACKET_MASK 0x3f /* Packet number mask */
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/* Bank 2, Offset 0x6: Pointer Register */
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#define PTR 0x6
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#define PTR_MASK 0x07ff /* Address accessible within TX/RX */
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#define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */
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#define PTR_ETEN 0x1000 /* Enable early TX underrun detection */
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#define PTR_READ 0x2000 /* Set read/write */
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#define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */
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#define PTR_RCV 0x8000 /* Read/write to/from RX/TX */
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/* Bank 2, Offset 0x8: Data Registers */
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#define DATA0 0x8
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#define DATA1 0xa
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/* Bank 2, Offset 0xc: Interrupt Status Registers */
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#define IST 0xc /* read only */
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#define ACK 0xc /* write only */
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#define MSK 0xd
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#define RCV_INT 0x0001 /* RX */
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#define TX_INT 0x0002 /* TX */
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#define TX_EMPTY_INT 0x0004 /* TX empty */
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#define ALLOC_INT 0x0008 /* Allocation complete */
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#define RX_OVRN_INT 0x0010 /* RX overrun */
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#define EPH_INT 0x0020 /* EPH interrupt */
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#define ERCV_INT 0x0040 /* Early RX */
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#define MD_INT 0x0080 /* MII */
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#define IST_PRINTF "\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \
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"\05RX_OVRN\06EPH\07ERCV\10MD"
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/* Bank 3, Offset 0x0: Multicast Table Registers */
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#define MT 0x0
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/* Bank 3, Offset 0x8: Management Interface */
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#define MGMT 0x8
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#define MGMT_MDO 0x0001 /* MII management output */
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#define MGMT_MDI 0x0002 /* MII management input */
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#define MGMT_MCLK 0x0004 /* MII management clock */
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#define MGMT_MDOE 0x0008 /* MII management output enable */
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#define MGMT_MSK_CRS100 0x4000 /* Disable CRS100 detection during TX */
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/* Bank 3, Offset 0xa: Revision Register */
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#define REV 0xa
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#define REV_CHIP_MASK 0x00f0 /* Chip ID */
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#define REV_CHIP_SHIFT 4
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#define REV_REV_MASK 0x000f /* Revision ID */
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#define REV_REV_SHIFT 0
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#define REV_CHIP_9192 3
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#define REV_CHIP_9194 4
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#define REV_CHIP_9195 5
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#define REV_CHIP_9196 6
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#define REV_CHIP_91100 7
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#define REV_CHIP_91100FD 8
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#define REV_CHIP_91110FD 9
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/* Bank 3, Offset 0xc: Early RCV Register */
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#define ERCV 0xc
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#define ERCV_THRESHOLD_MASK 0x001f /* ERCV int threshold (64b chunks) */
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#define ERCV_RCV_DISCARD 0x0080 /* Discard packet being received */
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/* Control Byte */
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#define CTRL_CRC 0x10 /* Frame has CRC */
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#define CTRL_ODD 0x20 /* Frame has odd byte count */
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/* Receive Frame Status */
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#define RX_MULTCAST 0x0001 /* Frame was multicast */
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#define RX_HASH_MASK 0x007e /* Hash value for multicast */
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#define RX_HASH_SHIFT 1
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#define RX_TOOSHORT 0x0400 /* Frame was too short */
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#define RX_TOOLNG 0x0800 /* Frame was too long */
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#define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */
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#define RX_BADCRC 0x2000 /* Frame failed CRC */
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#define RX_BROADCAST 0x4000 /* Frame was broadcast */
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#define RX_ALGNERR 0x8000 /* Frame had alignment error */
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#define RX_LEN_MASK 0x07ff
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/* Length of status word + byte count + control bytes for packets */
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#define PKT_CTRL_DATA_LEN 6
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/* Number of times to spin on TX allocations */
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#define TX_ALLOC_WAIT_TIME 1000
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#endif /* IF_SMCREG_H_ */
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