1368987ae4
the x86 tree. The $PIR code is still only enabled on i386 and not amd64. While here, make the qpi(4) driver on conditional on 'device pci'.
61 lines
2.4 KiB
C
61 lines
2.4 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __X86_PCI_CFGREG_H__
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#define __X86_PCI_CFGREG_H__
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#define CONF1_ADDR_PORT 0x0cf8
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#define CONF1_DATA_PORT 0x0cfc
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#define CONF1_ENABLE 0x80000000ul
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#define CONF1_ENABLE_CHK 0x80000000ul
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#define CONF1_ENABLE_MSK 0x7f000000ul
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#define CONF1_ENABLE_CHK1 0xff000001ul
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#define CONF1_ENABLE_MSK1 0x80000001ul
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#define CONF1_ENABLE_RES1 0x80000000ul
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#define CONF2_ENABLE_PORT 0x0cf8
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#define CONF2_FORWARD_PORT 0x0cfa
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#define CONF2_ENABLE_CHK 0x0e
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#define CONF2_ENABLE_RES 0x0e
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u_long hostb_alloc_start(int type, u_long start, u_long end, u_long count);
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int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
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int pci_cfgregopen(void);
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u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
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void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
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#ifdef __HAVE_PIR
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void pci_pir_open(void);
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int pci_pir_probe(int bus, int require_parse);
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int pci_pir_route_interrupt(int bus, int device, int func, int pin);
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#endif
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#endif /* !__X86_PCI_CFGREG_H__ */
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