f0fdcfe247
by adding an argument to the VM_SUSPEND ioctl that specifies how the virtual machine should be suspended, viz. VM_SUSPEND_RESET or VM_SUSPEND_POWEROFF. The disposition of VM_SUSPEND is also made available to the exit handler via the 'u.suspended' member of 'struct vm_exit'. This capability is exposed via the '--force-reset' and '--force-poweroff' arguments to /usr/sbin/bhyvectl. Discussed with: grehan@
285 lines
7.0 KiB
C
285 lines
7.0 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_DEV_H_
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#define _VMM_DEV_H_
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#ifdef _KERNEL
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void vmmdev_init(void);
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int vmmdev_cleanup(void);
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#endif
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struct vm_memory_segment {
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vm_paddr_t gpa; /* in */
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size_t len;
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int wired;
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};
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struct vm_register {
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int cpuid;
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int regnum; /* enum vm_reg_name */
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uint64_t regval;
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};
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struct vm_seg_desc { /* data or code segment */
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int cpuid;
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int regnum; /* enum vm_reg_name */
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struct seg_desc desc;
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};
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struct vm_run {
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int cpuid;
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uint64_t rip; /* start running here */
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struct vm_exit vm_exit;
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};
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struct vm_exception {
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int cpuid;
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int vector;
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uint32_t error_code;
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int error_code_valid;
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};
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struct vm_lapic_msi {
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uint64_t msg;
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uint64_t addr;
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};
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struct vm_lapic_irq {
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int cpuid;
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int vector;
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};
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struct vm_ioapic_irq {
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int irq;
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};
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struct vm_isa_irq {
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int atpic_irq;
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int ioapic_irq;
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};
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struct vm_capability {
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int cpuid;
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enum vm_cap_type captype;
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int capval;
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int allcpus;
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};
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struct vm_pptdev {
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int bus;
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int slot;
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int func;
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};
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struct vm_pptdev_mmio {
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int bus;
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int slot;
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int func;
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vm_paddr_t gpa;
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vm_paddr_t hpa;
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size_t len;
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};
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struct vm_pptdev_msi {
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int vcpu;
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int bus;
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int slot;
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int func;
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int numvec; /* 0 means disabled */
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uint64_t msg;
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uint64_t addr;
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};
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struct vm_pptdev_msix {
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int vcpu;
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int bus;
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int slot;
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int func;
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int idx;
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uint64_t msg;
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uint32_t vector_control;
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uint64_t addr;
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};
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struct vm_nmi {
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int cpuid;
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};
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#define MAX_VM_STATS 64
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struct vm_stats {
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int cpuid; /* in */
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int num_entries; /* out */
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struct timeval tv;
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uint64_t statbuf[MAX_VM_STATS];
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};
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struct vm_stat_desc {
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int index; /* in */
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char desc[128]; /* out */
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};
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struct vm_x2apic {
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int cpuid;
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enum x2apic_state state;
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};
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struct vm_gpa_pte {
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uint64_t gpa; /* in */
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uint64_t pte[4]; /* out */
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int ptenum;
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};
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struct vm_hpet_cap {
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uint32_t capabilities; /* lower 32 bits of HPET capabilities */
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};
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struct vm_suspend {
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enum vm_suspend_how how;
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};
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enum {
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/* general routines */
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IOCNUM_ABIVERS = 0,
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IOCNUM_RUN = 1,
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IOCNUM_SET_CAPABILITY = 2,
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IOCNUM_GET_CAPABILITY = 3,
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IOCNUM_SUSPEND = 4,
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/* memory apis */
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IOCNUM_MAP_MEMORY = 10,
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IOCNUM_GET_MEMORY_SEG = 11,
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IOCNUM_GET_GPA_PMAP = 12,
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/* register/state accessors */
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IOCNUM_SET_REGISTER = 20,
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IOCNUM_GET_REGISTER = 21,
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IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
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IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
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/* interrupt injection */
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IOCNUM_INJECT_EXCEPTION = 30,
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IOCNUM_LAPIC_IRQ = 31,
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IOCNUM_INJECT_NMI = 32,
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IOCNUM_IOAPIC_ASSERT_IRQ = 33,
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IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
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IOCNUM_IOAPIC_PULSE_IRQ = 35,
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IOCNUM_LAPIC_MSI = 36,
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IOCNUM_LAPIC_LOCAL_IRQ = 37,
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IOCNUM_IOAPIC_PINCOUNT = 38,
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/* PCI pass-thru */
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IOCNUM_BIND_PPTDEV = 40,
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IOCNUM_UNBIND_PPTDEV = 41,
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IOCNUM_MAP_PPTDEV_MMIO = 42,
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IOCNUM_PPTDEV_MSI = 43,
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IOCNUM_PPTDEV_MSIX = 44,
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/* statistics */
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IOCNUM_VM_STATS = 50,
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IOCNUM_VM_STAT_DESC = 51,
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/* kernel device state */
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IOCNUM_SET_X2APIC_STATE = 60,
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IOCNUM_GET_X2APIC_STATE = 61,
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IOCNUM_GET_HPET_CAPABILITIES = 62,
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/* legacy interrupt injection */
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IOCNUM_ISA_ASSERT_IRQ = 80,
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IOCNUM_ISA_DEASSERT_IRQ = 81,
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IOCNUM_ISA_PULSE_IRQ = 82,
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};
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#define VM_RUN \
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_IOWR('v', IOCNUM_RUN, struct vm_run)
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#define VM_SUSPEND \
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_IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
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#define VM_MAP_MEMORY \
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_IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
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#define VM_GET_MEMORY_SEG \
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_IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
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#define VM_SET_REGISTER \
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_IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
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#define VM_GET_REGISTER \
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_IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
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#define VM_SET_SEGMENT_DESCRIPTOR \
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_IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
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#define VM_GET_SEGMENT_DESCRIPTOR \
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_IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
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#define VM_INJECT_EXCEPTION \
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_IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
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#define VM_LAPIC_IRQ \
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_IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
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#define VM_LAPIC_LOCAL_IRQ \
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_IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
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#define VM_LAPIC_MSI \
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_IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
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#define VM_IOAPIC_ASSERT_IRQ \
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_IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_DEASSERT_IRQ \
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_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_PULSE_IRQ \
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_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_PINCOUNT \
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_IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
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#define VM_ISA_ASSERT_IRQ \
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_IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
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#define VM_ISA_DEASSERT_IRQ \
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_IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
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#define VM_ISA_PULSE_IRQ \
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_IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
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#define VM_SET_CAPABILITY \
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_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
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#define VM_GET_CAPABILITY \
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_IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
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#define VM_BIND_PPTDEV \
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_IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
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#define VM_UNBIND_PPTDEV \
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_IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
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#define VM_MAP_PPTDEV_MMIO \
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_IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
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#define VM_PPTDEV_MSI \
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_IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
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#define VM_PPTDEV_MSIX \
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_IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
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#define VM_INJECT_NMI \
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_IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
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#define VM_STATS \
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_IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
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#define VM_STAT_DESC \
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_IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
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#define VM_SET_X2APIC_STATE \
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_IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
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#define VM_GET_X2APIC_STATE \
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_IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
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#define VM_GET_HPET_CAPABILITIES \
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_IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
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#define VM_GET_GPA_PMAP \
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_IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
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#endif
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