97 lines
3.7 KiB
C
97 lines
3.7 KiB
C
/*-
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* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Altera mSGDMA registers. */
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#define DMA_STATUS 0x00
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#define STATUS_RESETTING (1 << 6)
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#define DMA_CONTROL 0x04
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#define CONTROL_GIEM (1 << 4) /* Global Interrupt Enable Mask */
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#define CONTROL_RESET (1 << 1) /* Reset Dispatcher */
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/* Descriptor fields. */
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#define CONTROL_GO (1 << 31) /* Commit all the descriptor info */
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#define CONTROL_OWN (1 << 30) /* Owned by hardware (prefetcher-enabled only) */
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#define CONTROL_EDE (1 << 24) /* Early done enable */
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#define CONTROL_ERR_S 16 /* Transmit Error, Error IRQ Enable */
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#define CONTROL_ERR_M (0xff << CONTROL_ERR_S)
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#define CONTROL_ET_IRQ_EN (1 << 15) /* Early Termination IRQ Enable */
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#define CONTROL_TC_IRQ_EN (1 << 14) /* Transfer Complete IRQ Enable */
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#define CONTROL_END_ON_EOP (1 << 12) /* End on EOP */
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#define CONTROL_PARK_WR (1 << 11) /* Park Writes */
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#define CONTROL_PARK_RD (1 << 10) /* Park Reads */
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#define CONTROL_GEN_EOP (1 << 9) /* Generate EOP */
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#define CONTROL_GEN_SOP (1 << 8) /* Generate SOP */
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#define CONTROL_TX_CHANNEL_S 0 /* Transmit Channel */
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#define CONTROL_TX_CHANNEL_M (0xff << CONTROL_TRANSMIT_CH_S)
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/* Prefetcher */
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#define PF_CONTROL 0x00
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#define PF_CONTROL_GIEM (1 << 3)
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#define PF_CONTROL_RESET (1 << 2)
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#define PF_CONTROL_DESC_POLL_EN (1 << 1)
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#define PF_CONTROL_RUN (1 << 0)
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#define PF_NEXT_LO 0x04
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#define PF_NEXT_HI 0x08
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#define PF_POLL_FREQ 0x0C
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#define PF_STATUS 0x10
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#define PF_STATUS_IRQ (1 << 0)
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#define READ4(_sc, _reg) \
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le32toh(bus_space_read_4(_sc->bst, _sc->bsh, _reg))
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#define WRITE4(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst, _sc->bsh, _reg, htole32(_val))
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#define READ4_DESC(_sc, _reg) \
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le32toh(bus_space_read_4(_sc->bst_d, _sc->bsh_d, _reg))
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#define WRITE4_DESC(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst_d, _sc->bsh_d, _reg, htole32(_val))
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/* Prefetcher-disabled descriptor format. */
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struct msgdma_desc_nonpf {
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uint32_t src_addr;
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uint32_t dst_addr;
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uint32_t length;
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uint32_t control;
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};
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/* Prefetcher-enabled descriptor format. */
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struct msgdma_desc {
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uint32_t read_lo;
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uint32_t write_lo;
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uint32_t length;
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uint32_t next;
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uint32_t transferred;
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uint32_t status;
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uint32_t reserved;
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uint32_t control;
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};
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