590 lines
18 KiB
C
590 lines
18 KiB
C
/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: if_wbreg.h,v 1.3 1999/05/06 15:32:52 wpaul Exp $
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*/
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/*
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* Winbond register definitions.
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*/
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#define WB_BUSCTL 0x00 /* bus control */
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#define WB_TXSTART 0x04 /* tx start demand */
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#define WB_RXSTART 0x08 /* rx start demand */
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#define WB_RXADDR 0x0C /* rx descriptor list start addr */
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#define WB_TXADDR 0x10 /* tx descriptor list start addr */
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#define WB_ISR 0x14 /* interrupt status register */
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#define WB_NETCFG 0x18 /* network config register */
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#define WB_IMR 0x1C /* interrupt mask */
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#define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */
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#define WB_SIO 0x24 /* MII and ROM/EEPROM access */
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#define WB_BOOTROMADDR 0x28
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#define WB_TIMER 0x2C /* general timer */
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#define WB_CURRXCTL 0x30 /* current RX descriptor */
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#define WB_CURRXBUF 0x34 /* current RX buffer */
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#define WB_MAR0 0x38 /* multicast filter 0 */
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#define WB_MAR1 0x3C /* multicast filter 1 */
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#define WB_NODE0 0x40 /* station address 0 */
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#define WB_NODE1 0x44 /* station address 1 */
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#define WB_BOOTROMSIZE 0x48 /* boot ROM size */
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#define WB_CURTXCTL 0x4C /* current TX descriptor */
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#define WB_CURTXBUF 0x50 /* current TX buffer */
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/*
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* Bus control bits.
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*/
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#define WB_BUSCTL_RESET 0x00000001
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#define WB_BUSCTL_ARBITRATION 0x00000002
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#define WB_BUSCTL_SKIPLEN 0x0000007C
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#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
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#define WB_BUSCTL_BURSTLEN 0x00003F00
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#define WB_BUSCTL_CACHEALIGN 0x0000C000
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#define WB_BUSCTL_DES_BIGENDIAN 0x00100000
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#define WB_BUSCTL_WAIT 0x00200000
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#define WB_SKIPLEN_1LONG 0x00000004
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#define WB_SKIPLEN_2LONG 0x00000008
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#define WB_SKIPLEN_3LONG 0x00000010
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#define WB_SKIPLEN_4LONG 0x00000020
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#define WB_SKIPLEN_5LONG 0x00000040
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#define WB_CACHEALIGN_8LONG 0x00004000
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#define WB_CACHEALIGN_16LONG 0x00008000
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#define WB_CACHEALIGN_32LONG 0x0000C000
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#define WB_BURSTLEN_USECA 0x00000000
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#define WB_BURSTLEN_1LONG 0x00000100
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#define WB_BURSTLEN_2LONG 0x00000200
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#define WB_BURSTLEN_4LONG 0x00000400
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#define WB_BURSTLEN_8LONG 0x00000800
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#define WB_BURSTLEN_16LONG 0x00001000
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#define WB_BURSTLEN_32LONG 0x00002000
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#define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
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WB_BURSTLEN_8LONG)
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/*
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* Interrupt status bits.
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*/
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#define WB_ISR_TX_OK 0x00000001
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#define WB_ISR_TX_IDLE 0x00000002
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#define WB_ISR_TX_NOBUF 0x00000004
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#define WB_ISR_RX_EARLY 0x00000008
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#define WB_ISR_RX_ERR 0x00000010
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#define WB_ISR_TX_UNDERRUN 0x00000020
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#define WB_ISR_RX_OK 0x00000040
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#define WB_ISR_RX_NOBUF 0x00000080
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#define WB_ISR_RX_IDLE 0x00000100
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#define WB_ISR_TX_EARLY 0x00000400
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#define WB_ISR_TIMER_EXPIRED 0x00000800
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#define WB_ISR_BUS_ERR 0x00002000
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#define WB_ISR_ABNORMAL 0x00008000
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#define WB_ISR_NORMAL 0x00010000
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#define WB_ISR_RX_STATE 0x000E0000
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#define WB_ISR_TX_STATE 0x00700000
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#define WB_ISR_BUSERRTYPE 0x03800000
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/*
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* The RX_STATE and TX_STATE fields are not described anywhere in the
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* Winbond datasheet, however it appears that the Winbond chip is an
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* attempt at a DEC 'tulip' clone, hence the ISR register is identical
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* to that of the tulip chip and we can steal the bit definitions from
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* the tulip documentation.
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*/
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#define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
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#define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
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#define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
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#define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
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#define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
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#define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
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#define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
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#define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
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#define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */
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#define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
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#define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
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#define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
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#define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
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#define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
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#define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
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#define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
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/*
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* Network config bits.
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*/
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#define WB_NETCFG_RX_ON 0x00000002
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#define WB_NETCFG_RX_ALLPHYS 0x00000008
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#define WB_NETCFG_RX_MULTI 0x00000010
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#define WB_NETCFG_RX_BROAD 0x00000020
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#define WB_NETCFG_RX_RUNT 0x00000040
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#define WB_NETCFG_RX_ERR 0x00000080
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#define WB_NETCFG_FULLDUPLEX 0x00000200
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#define WB_NETCFG_LOOPBACK 0x00000C00
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#define WB_NETCFG_TX_ON 0x00002000
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#define WB_NETCFG_TX_THRESH 0x001FC000
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#define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000
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#define WB_NETCFG_100MBPS 0x20000000
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#define WB_NETCFG_TX_EARLY_ON 0x40000000
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#define WB_NETCFG_RX_EARLY_ON 0x80000000
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/*
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* The tx threshold can be adjusted in increments of 32 bytes.
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*/
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#define WB_TXTHRESH(x) ((x >> 5) << 14)
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#define WB_TXTHRESH_CHUNK 32
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#define WB_TXTHRESH_INIT 0 /*72*/
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/*
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* Interrupt mask bits.
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*/
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#define WB_IMR_TX_OK 0x00000001
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#define WB_IMR_TX_IDLE 0x00000002
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#define WB_IMR_TX_NOBUF 0x00000004
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#define WB_IMR_RX_EARLY 0x00000008
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#define WB_IMR_RX_ERR 0x00000010
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#define WB_IMR_TX_UNDERRUN 0x00000020
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#define WB_IMR_RX_OK 0x00000040
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#define WB_IMR_RX_NOBUF 0x00000080
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#define WB_IMR_RX_IDLE 0x00000100
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#define WB_IMR_TX_EARLY 0x00000400
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#define WB_IMR_TIMER_EXPIRED 0x00000800
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#define WB_IMR_BUS_ERR 0x00002000
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#define WB_IMR_ABNORMAL 0x00008000
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#define WB_IMR_NORMAL 0x00010000
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#define WB_INTRS \
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(WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \
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WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \
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WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
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/*
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* Serial I/O (EEPROM/ROM) bits.
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*/
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#define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */
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#define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */
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#define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
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#define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
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#define WB_SIO_ROMDATA4 0x00000010
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#define WB_SIO_ROMDATA5 0x00000020
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#define WB_SIO_ROMDATA6 0x00000040
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#define WB_SIO_ROMDATA7 0x00000080
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#define WB_SIO_ROMCTL_WRITE 0x00000200
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#define WB_SIO_ROMCTL_READ 0x00000400
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#define WB_SIO_EESEL 0x00000800
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#define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */
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#define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */
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#define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */
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#define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */
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#define WB_EECMD_WRITE 0x140
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#define WB_EECMD_READ 0x180
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#define WB_EECMD_ERASE 0x1c0
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/*
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* Winbond TX/RX descriptor structure.
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*/
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struct wb_desc {
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u_int32_t wb_status;
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u_int32_t wb_ctl;
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u_int32_t wb_ptr1;
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u_int32_t wb_ptr2;
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};
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#define wb_data wb_ptr1
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#define wb_next wb_ptr2
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#define WB_RXSTAT_CRCERR 0x00000002
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#define WB_RXSTAT_DRIBBLE 0x00000004
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#define WB_RXSTAT_MIIERR 0x00000008
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#define WB_RXSTAT_LATEEVENT 0x00000040
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#define WB_RXSTAT_GIANT 0x00000080
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#define WB_RXSTAT_LASTFRAG 0x00000100
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#define WB_RXSTAT_FIRSTFRAG 0x00000200
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#define WB_RXSTAT_MULTICAST 0x00000400
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#define WB_RXSTAT_RUNT 0x00000800
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#define WB_RXSTAT_RXTYPE 0x00003000
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#define WB_RXSTAT_RXERR 0x00008000
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#define WB_RXSTAT_RXLEN 0x3FFF0000
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#define WB_RXSTAT_RXCMP 0x40000000
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#define WB_RXSTAT_OWN 0x80000000
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#define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16)
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#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
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#define WB_RXCTL_BUFLEN1 0x00000FFF
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#define WB_RXCTL_BUFLEN2 0x00FFF000
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#define WB_RXCTL_RLINK 0x01000000
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#define WB_RXCTL_RLAST 0x02000000
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#define WB_TXSTAT_DEFER 0x00000001
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#define WB_TXSTAT_UNDERRUN 0x00000002
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#define WB_TXSTAT_COLLCNT 0x00000078
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#define WB_TXSTAT_SQE 0x00000080
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#define WB_TXSTAT_ABORT 0x00000100
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#define WB_TXSTAT_LATECOLL 0x00000200
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#define WB_TXSTAT_NOCARRIER 0x00000400
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#define WB_TXSTAT_CARRLOST 0x00000800
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#define WB_TXSTAT_TXERR 0x00001000
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#define WB_TXSTAT_OWN 0x80000000
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#define WB_TXCTL_BUFLEN1 0x000007FF
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#define WB_TXCTL_BUFLEN2 0x003FF800
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#define WB_TXCTL_PAD 0x00800000
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#define WB_TXCTL_TLINK 0x01000000
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#define WB_TXCTL_TLAST 0x02000000
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#define WB_TXCTL_NOCRC 0x08000000
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#define WB_TXCTL_FIRSTFRAG 0x20000000
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#define WB_TXCTL_LASTFRAG 0x40000000
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#define WB_TXCTL_FINT 0x80000000
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#define WB_MAXFRAGS 16
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#define WB_RX_LIST_CNT 64
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#define WB_TX_LIST_CNT 128
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#define WB_MIN_FRAMELEN 60
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#define ETHER_ALIGN 2
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/*
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* A transmit 'super descriptor' is actually WB_MAXFRAGS regular
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* descriptors clumped together. The idea here is to emulate the
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* multi-fragment descriptor layout found in devices such as the
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* Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
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* The advantage to using this scheme is that it avoids buffer copies.
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* The disadvantage is that there's a certain amount of overhead due
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* to the fact that each 'fragment' is 16 bytes long. In my tests,
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* this limits top speed to about 10.5MB/sec. It should be more like
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* 11.5MB/sec. However, the upshot is that you can achieve better
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* results on slower machines: a Pentium 200 can pump out packets at
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* same speed as a PII 400.
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*/
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struct wb_txdesc {
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struct wb_desc wb_frag[WB_MAXFRAGS];
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};
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#define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
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#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
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#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
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#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
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#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
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#define WB_UNSENT 0x1234
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struct wb_list_data {
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struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
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struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
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};
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struct wb_chain {
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struct wb_txdesc *wb_ptr;
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struct mbuf *wb_mbuf;
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struct wb_chain *wb_nextdesc;
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u_int8_t wb_lastdesc;
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};
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struct wb_chain_onefrag {
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struct wb_desc *wb_ptr;
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struct mbuf *wb_mbuf;
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struct wb_chain_onefrag *wb_nextdesc;
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u_int8_t wb_rlast;
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};
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struct wb_chain_data {
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u_int8_t wb_pad[WB_MIN_FRAMELEN];
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struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
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struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];
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struct wb_chain_onefrag *wb_rx_head;
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struct wb_chain *wb_tx_head;
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struct wb_chain *wb_tx_tail;
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struct wb_chain *wb_tx_free;
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};
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struct wb_type {
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u_int16_t wb_vid;
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u_int16_t wb_did;
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char *wb_name;
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};
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struct wb_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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u_int8_t mii_phyaddr;
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u_int8_t mii_regaddr;
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u_int8_t mii_turnaround;
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u_int16_t mii_data;
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};
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/*
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* MII constants
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*/
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#define WB_MII_STARTDELIM 0x01
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#define WB_MII_READOP 0x02
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#define WB_MII_WRITEOP 0x01
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#define WB_MII_TURNAROUND 0x02
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#define WB_FLAG_FORCEDELAY 1
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#define WB_FLAG_SCHEDDELAY 2
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#define WB_FLAG_DELAYTIMEO 3
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struct wb_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia ifmedia; /* media info */
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bus_space_handle_t wb_bhandle;
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bus_space_tag_t wb_btag;
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struct wb_type *wb_info; /* 3Com adapter info */
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struct wb_type *wb_pinfo; /* phy info */
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u_int8_t wb_unit; /* interface number */
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u_int8_t wb_type;
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u_int8_t wb_phy_addr; /* PHY address */
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u_int8_t wb_tx_pend; /* TX pending */
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u_int8_t wb_want_auto;
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u_int8_t wb_autoneg;
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u_int16_t wb_txthresh;
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caddr_t wb_ldata_ptr;
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struct wb_list_data *wb_ldata;
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struct wb_chain_data wb_cdata;
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};
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
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#define WB_TIMEOUT 1000
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/*
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* General constants that are fun to know.
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*
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* Winbond PCI vendor ID
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*/
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#define WB_VENDORID 0x1050
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/*
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* Winbond device IDs.
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*/
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#define WB_DEVICEID_840F 0x0840
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/*
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* Compex vendor ID.
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*/
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#define CP_VENDORID 0x11F6
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/*
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* Compex device IDs.
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*/
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#define CP_DEVICEID_RL100 0x2011
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/*
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* Texas Instruments PHY identifiers
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*/
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#define TI_PHY_VENDORID 0x4000
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#define TI_PHY_10BT 0x501F
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#define TI_PHY_100VGPMI 0x502F
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/*
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* These ID values are for the NS DP83840A 10/100 PHY
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*/
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#define NS_PHY_VENDORID 0x2000
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#define NS_PHY_83840A 0x5C0F
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/*
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* Level 1 10/100 PHY
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|
*/
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#define LEVEL1_PHY_VENDORID 0x7810
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|
#define LEVEL1_PHY_LXT970 0x000F
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|
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/*
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* Intel 82555 10/100 PHY
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|
*/
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|
#define INTEL_PHY_VENDORID 0x0A28
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#define INTEL_PHY_82555 0x015F
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|
|
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/*
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|
* SEEQ 80220 10/100 PHY
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|
*/
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|
#define SEEQ_PHY_VENDORID 0x0016
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#define SEEQ_PHY_80220 0xF83F
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|
|
|
|
/*
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* PCI low memory base and low I/O base register, and
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|
* other PCI registers. Note: some are only available on
|
|
* the 3c905B, in particular those that related to power management.
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|
*/
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|
|
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#define WB_PCI_VENDOR_ID 0x00
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#define WB_PCI_DEVICE_ID 0x02
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#define WB_PCI_COMMAND 0x04
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#define WB_PCI_STATUS 0x06
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|
#define WB_PCI_CLASSCODE 0x09
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|
#define WB_PCI_LATENCY_TIMER 0x0D
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#define WB_PCI_HEADER_TYPE 0x0E
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#define WB_PCI_LOIO 0x10
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#define WB_PCI_LOMEM 0x14
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|
#define WB_PCI_BIOSROM 0x30
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|
#define WB_PCI_INTLINE 0x3C
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#define WB_PCI_INTPIN 0x3D
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#define WB_PCI_MINGNT 0x3E
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#define WB_PCI_MINLAT 0x0F
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#define WB_PCI_RESETOPT 0x48
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#define WB_PCI_EEPROM_DATA 0x4C
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|
|
|
/* power management registers */
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|
#define WB_PCI_CAPID 0xDC /* 8 bits */
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#define WB_PCI_NEXTPTR 0xDD /* 8 bits */
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#define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */
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#define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
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|
|
|
#define WB_PSTATE_MASK 0x0003
|
|
#define WB_PSTATE_D0 0x0000
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|
#define WB_PSTATE_D1 0x0002
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|
#define WB_PSTATE_D2 0x0002
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|
#define WB_PSTATE_D3 0x0003
|
|
#define WB_PME_EN 0x0010
|
|
#define WB_PME_STATUS 0x8000
|
|
|
|
#define PHY_UNKNOWN 6
|
|
|
|
#define WB_PHYADDR_MIN 0x00
|
|
#define WB_PHYADDR_MAX 0x1F
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|
|
|
#define PHY_BMCR 0x00
|
|
#define PHY_BMSR 0x01
|
|
#define PHY_VENID 0x02
|
|
#define PHY_DEVID 0x03
|
|
#define PHY_ANAR 0x04
|
|
#define PHY_LPAR 0x05
|
|
#define PHY_ANEXP 0x06
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|
|
|
#define PHY_ANAR_NEXTPAGE 0x8000
|
|
#define PHY_ANAR_RSVD0 0x4000
|
|
#define PHY_ANAR_TLRFLT 0x2000
|
|
#define PHY_ANAR_RSVD1 0x1000
|
|
#define PHY_ANAR_RSVD2 0x0800
|
|
#define PHY_ANAR_RSVD3 0x0400
|
|
#define PHY_ANAR_100BT4 0x0200
|
|
#define PHY_ANAR_100BTXFULL 0x0100
|
|
#define PHY_ANAR_100BTXHALF 0x0080
|
|
#define PHY_ANAR_10BTFULL 0x0040
|
|
#define PHY_ANAR_10BTHALF 0x0020
|
|
#define PHY_ANAR_PROTO4 0x0010
|
|
#define PHY_ANAR_PROTO3 0x0008
|
|
#define PHY_ANAR_PROTO2 0x0004
|
|
#define PHY_ANAR_PROTO1 0x0002
|
|
#define PHY_ANAR_PROTO0 0x0001
|
|
|
|
/*
|
|
* These are the register definitions for the PHY (physical layer
|
|
* interface chip).
|
|
*/
|
|
/*
|
|
* PHY BMCR Basic Mode Control Register
|
|
*/
|
|
#define PHY_BMCR_RESET 0x8000
|
|
#define PHY_BMCR_LOOPBK 0x4000
|
|
#define PHY_BMCR_SPEEDSEL 0x2000
|
|
#define PHY_BMCR_AUTONEGENBL 0x1000
|
|
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
|
|
#define PHY_BMCR_ISOLATE 0x0400
|
|
#define PHY_BMCR_AUTONEGRSTR 0x0200
|
|
#define PHY_BMCR_DUPLEX 0x0100
|
|
#define PHY_BMCR_COLLTEST 0x0080
|
|
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
|
|
/*
|
|
* RESET: 1 == software reset, 0 == normal operation
|
|
* Resets status and control registers to default values.
|
|
* Relatches all hardware config values.
|
|
*
|
|
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
|
|
*
|
|
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
|
|
* Link speed is selected byt his bit or if auto-negotiation if bit
|
|
* 12 (AUTONEGENBL) is set (in which case the value of this register
|
|
* is ignored).
|
|
*
|
|
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
|
|
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
|
|
* determine speed and mode. Should be cleared and then set if PHY configured
|
|
* for no autoneg on startup.
|
|
*
|
|
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
|
|
*
|
|
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
|
|
*
|
|
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
|
|
*
|
|
* COLLTEST: 1 == collision test enabled, 0 == normal operation
|
|
*/
|
|
|
|
/*
|
|
* PHY, BMSR Basic Mode Status Register
|
|
*/
|
|
#define PHY_BMSR_100BT4 0x8000
|
|
#define PHY_BMSR_100BTXFULL 0x4000
|
|
#define PHY_BMSR_100BTXHALF 0x2000
|
|
#define PHY_BMSR_10BTFULL 0x1000
|
|
#define PHY_BMSR_10BTHALF 0x0800
|
|
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
|
|
#define PHY_BMSR_MFPRESUP 0x0040
|
|
#define PHY_BMSR_AUTONEGCOMP 0x0020
|
|
#define PHY_BMSR_REMFAULT 0x0010
|
|
#define PHY_BMSR_CANAUTONEG 0x0008
|
|
#define PHY_BMSR_LINKSTAT 0x0004
|
|
#define PHY_BMSR_JABBER 0x0002
|
|
#define PHY_BMSR_EXTENDED 0x0001
|
|
|
|
#ifdef __alpha__
|
|
#undef vtophys
|
|
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
|
#endif
|