f2972d7eb8
controllers (PDC203** PDC206**). This also adds preliminary support for the Promise SX4/SX4000 but *only* as a "normal" Promise ATA controller (ATA RAID's are supported though but only RAID0, RAID1 and RAID0+1). This cuts off yet another 5-8% of the command overhead on promise controllers, making them the fastest we have ever had support for. Work is now continuing to add support for this in ATA RAID, to accellerate ATA RAID quite a bit on these controllers, and especially the SX4/SX4000 series as they have quite a few tricks in there.. This commit also adds a few fixes to the SATA code needed for proper support.
852 lines
25 KiB
C
852 lines
25 KiB
C
/*-
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* Copyright (c) 1998 - 2004 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ata.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/ata/ata-all.h>
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/* prototypes */
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static int ata_generic_transaction(struct ata_request *);
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static void ata_generic_interrupt(void *);
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static void ata_generic_reset(struct ata_channel *);
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static int ata_wait(struct ata_device *, u_int8_t);
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/*static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);*/
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static void ata_pio_read(struct ata_request *, int);
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static void ata_pio_write(struct ata_request *, int);
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/* local vars */
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static int atadebug = 0;
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/*
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* low level ATA functions
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*/
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void
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ata_generic_hw(struct ata_channel *ch)
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{
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ch->hw.reset = ata_generic_reset;
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ch->hw.transaction = ata_generic_transaction;
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ch->hw.interrupt = ata_generic_interrupt;
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ch->hw.command = ata_generic_command;
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}
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/* must be called with ATA channel locked */
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static int
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ata_generic_transaction(struct ata_request *request)
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{
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struct ata_channel *ch = request->device->channel;
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/* safetybelt for HW that went away */
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if (!request->device->param || request->device->channel->flags&ATA_HWGONE) {
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request->result = ENXIO;
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return ATA_OP_FINISHED;
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}
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/* record the request as running */
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ch->running = request;
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ATA_DEBUG_RQ(request, "transaction");
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/* disable ATAPI DMA writes if HW doesn't support it */
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if ((ch->flags & ATA_ATAPI_DMA_RO) &&
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((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
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(ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
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request->flags &= ~ATA_R_DMA;
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switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
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/* ATA PIO data transfer and control commands */
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default:
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{
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/* record command direction here as our request might be gone later */
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int write = (request->flags & ATA_R_WRITE);
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/* issue command */
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if (ch->hw.command(request->device, request->u.ata.command,
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request->u.ata.lba, request->u.ata.count,
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request->u.ata.feature)) {
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ata_prtdev(request->device, "error issueing PIO command\n");
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request->result = EIO;
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break;
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}
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/* if write command output the data */
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if (write) {
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if (ata_wait(request->device,
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(ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
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ata_prtdev(request->device,"timeout waiting for write DRQ");
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request->result = EIO;
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break;
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}
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ata_pio_write(request, request->transfersize);
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}
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}
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/* return and wait for interrupt */
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return ATA_OP_CONTINUES;
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/* ATA DMA data transfer commands */
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case ATA_R_DMA:
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/* check sanity, setup SG list and DMA engine */
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if (ch->dma->load(request->device, request->data, request->bytecount,
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request->flags & ATA_R_READ)) {
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ata_prtdev(request->device, "setting up DMA failed\n");
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request->result = EIO;
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break;
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}
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/* issue command */
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if (ch->hw.command(request->device, request->u.ata.command,
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request->u.ata.lba, request->u.ata.count,
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request->u.ata.feature)) {
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ata_prtdev(request->device, "error issuing DMA command\n");
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request->result = EIO;
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break;
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}
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/* start DMA engine */
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if (ch->dma->start(ch)) {
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ata_prtdev(request->device, "error starting DMA\n");
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request->result = EIO;
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break;
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}
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/* return and wait for interrupt */
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return ATA_OP_CONTINUES;
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/* ATAPI PIO commands */
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case ATA_R_ATAPI:
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/* is this just a POLL DSC command ? */
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if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
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ATA_IDX_OUTB(ch, ATA_DRIVE,
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ATA_D_IBM | request->device->unit);
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DELAY(10);
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if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC))
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request->result = EBUSY;
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break;
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}
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/* start ATAPI operation */
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if (ch->hw.command(request->device, ATA_PACKET_CMD,
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request->transfersize << 8, 0, 0)) {
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ata_prtdev(request->device, "error issuing ATA PACKET command\n");
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request->result = EIO;
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break;
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}
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/* command interrupt device ? just return and wait for interrupt */
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if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
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return ATA_OP_CONTINUES;
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/* wait for ready to write ATAPI command block */
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{
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int timeout = 5000; /* might be less for fast devices */
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while (timeout--) {
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int reason = ATA_IDX_INB(ch, ATA_IREASON);
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int status = ATA_IDX_INB(ch, ATA_STATUS);
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if (((reason & (ATA_I_CMD | ATA_I_IN)) |
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(status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
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break;
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DELAY(20);
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}
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if (timeout <= 0) {
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ata_prtdev(request->device,
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"timeout waiting for ATAPI ready\n");
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request->result = EIO;
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break;
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}
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}
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/* this seems to be needed for some (slow) devices */
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DELAY(10);
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/* output actual command block */
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ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
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(int16_t *)request->u.atapi.ccb,
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(request->device->param->config & ATA_PROTO_MASK) ==
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ATA_PROTO_ATAPI_12 ? 6 : 8);
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/* return and wait for interrupt */
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return ATA_OP_CONTINUES;
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case ATA_R_ATAPI|ATA_R_DMA:
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/* is this just a POLL DSC command ? */
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if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
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ATA_IDX_OUTB(ch, ATA_DRIVE,
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ATA_D_IBM | request->device->unit);
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DELAY(10);
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if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC))
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request->result = EBUSY;
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break;
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}
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/* check sanity, setup SG list and DMA engine */
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if (ch->dma->load(request->device,
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request->data,
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request->bytecount,
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request->flags & ATA_R_READ)) {
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ata_prtdev(request->device, "setting up DMA failed\n");
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request->result = EIO;
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break;
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}
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/* start ATAPI operation */
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if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) {
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ata_prtdev(request->device, "error issuing ATAPI packet command\n");
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request->result = EIO;
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break;
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}
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/* wait for ready to write ATAPI command block */
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{
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int timeout = 5000; /* might be less for fast devices */
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while (timeout--) {
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int reason = ATA_IDX_INB(ch, ATA_IREASON);
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int status = ATA_IDX_INB(ch, ATA_STATUS);
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if (((reason & (ATA_I_CMD | ATA_I_IN)) |
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(status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
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break;
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DELAY(20);
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}
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if (timeout <= 0) {
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ata_prtdev(request->device,"timeout waiting for ATAPI ready\n");
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request->result = EIO;
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break;
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}
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}
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/* this seems to be needed for some (slow) devices */
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DELAY(10);
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/* output actual command block */
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ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
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(int16_t *)request->u.atapi.ccb,
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(request->device->param->config & ATA_PROTO_MASK) ==
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ATA_PROTO_ATAPI_12 ? 6 : 8);
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/* start DMA engine */
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if (ch->dma->start(ch)) {
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request->result = EIO;
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break;
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}
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/* return and wait for interrupt */
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return ATA_OP_CONTINUES;
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}
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/* request finish here */
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if (ch->dma->flags & ATA_DMA_ACTIVE)
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ch->dma->unload(ch);
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ch->running = NULL;
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return ATA_OP_FINISHED;
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}
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static void
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ata_generic_interrupt(void *data)
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{
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struct ata_channel *ch = (struct ata_channel *)data;
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struct ata_request *request = ch->running;
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int length;
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/* ignore this interrupt if there is no running request */
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if (!request) {
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if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
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u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
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u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
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if (bootverbose)
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ata_printf(ch, -1,
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"spurious interrupt - status=0x%02x error=0x%02x\n",
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status, error);
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ATA_UNLOCK_CH(ch);
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}
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else {
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if (bootverbose)
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ata_printf(ch, -1, "spurious interrupt - channel busy\n");
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}
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return;
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}
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ATA_DEBUG_RQ(request, "interrupt");
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/* ignore interrupt if device is busy */
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if (!(request->flags & ATA_R_TIMEOUT) &&
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ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
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DELAY(100);
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if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
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return;
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}
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ATA_DEBUG_RQ(request, "interrupt accepted");
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/* clear interrupt and get status */
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request->status = ATA_IDX_INB(ch, ATA_STATUS);
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/* register interrupt */
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if (!(request->flags & ATA_R_TIMEOUT))
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request->flags |= ATA_R_INTR_SEEN;
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switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
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/* ATA PIO data transfer and control commands */
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default:
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/* on control commands read back registers to the request struct */
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if (request->flags & ATA_R_CONTROL) {
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request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
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request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
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(ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
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(ATA_IDX_INB(ch, ATA_CYL_MSB) << 16);
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}
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/* if we got an error we are done with the HW */
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if (request->status & ATA_S_ERROR) {
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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break;
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}
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/* are we moving data ? */
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if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
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/* if read data get it */
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if (request->flags & ATA_R_READ)
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ata_pio_read(request, request->transfersize);
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/* update how far we've gotten */
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request->donecount += request->transfersize;
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/* do we need a scoop more ? */
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if (request->bytecount > request->donecount) {
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/* set this transfer size according to HW capabilities */
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request->transfersize =
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min((request->bytecount - request->donecount),
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request->transfersize);
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/* clear interrupt seen flag as we need to wait again */
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request->flags &= ~ATA_R_INTR_SEEN;
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/* if data write command, output the data */
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if (request->flags & ATA_R_WRITE) {
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/* if we get an error here we are done with the HW */
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if (ata_wait(request->device,
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(ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
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ata_prtdev(request->device,
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"timeout waiting for write DRQ");
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request->status = ATA_IDX_INB(ch, ATA_STATUS);
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break;
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}
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/* output data and return waiting for new interrupt */
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ata_pio_write(request, request->transfersize);
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return;
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}
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/* if data read command, return & wait for interrupt */
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if (request->flags & ATA_R_READ)
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return;
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}
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}
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/* done with HW */
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break;
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/* ATA DMA data transfer commands */
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case ATA_R_DMA:
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/* stop DMA engine and get status */
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if (ch->dma->stop)
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request->dmastat = ch->dma->stop(ch);
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/* did we get error or data */
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if (request->status & ATA_S_ERROR)
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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else if (request->dmastat & ATA_BMSTAT_ERROR)
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request->status |= ATA_S_ERROR;
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else
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request->donecount = request->bytecount;
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/* release SG list etc */
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ch->dma->unload(ch);
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/* done with HW */
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break;
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/* ATAPI PIO commands */
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case ATA_R_ATAPI:
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length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
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switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
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(request->status & ATA_S_DRQ)) {
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case ATAPI_P_CMDOUT:
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/* this seems to be needed for some (slow) devices */
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DELAY(10);
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if (!(request->status & ATA_S_DRQ)) {
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ata_prtdev(request->device, "command interrupt without DRQ\n");
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request->status = ATA_S_ERROR;
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break;
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}
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ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
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(request->device->param->config &
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ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
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/* return wait for interrupt */
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return;
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case ATAPI_P_WRITE:
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if (request->flags & ATA_R_READ) {
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request->status = ATA_S_ERROR;
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ata_prtdev(request->device,
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"%s trying to write on read buffer\n",
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ata_cmd2str(request));
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break;
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}
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ata_pio_write(request, length);
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request->donecount += length;
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/* set next transfer size according to HW capabilities */
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request->transfersize = min((request->bytecount-request->donecount),
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request->transfersize);
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/* return wait for interrupt */
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return;
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case ATAPI_P_READ:
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if (request->flags & ATA_R_WRITE) {
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request->status = ATA_S_ERROR;
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ata_prtdev(request->device,
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"%s trying to read on write buffer\n",
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ata_cmd2str(request));
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break;
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}
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ata_pio_read(request, length);
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request->donecount += length;
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/* set next transfer size according to HW capabilities */
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request->transfersize = min((request->bytecount-request->donecount),
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request->transfersize);
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/* return wait for interrupt */
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return;
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case ATAPI_P_DONEDRQ:
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ata_prtdev(request->device,
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"WARNING - %s DONEDRQ non conformant device\n",
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ata_cmd2str(request));
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if (request->flags & ATA_R_READ) {
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ata_pio_read(request, length);
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request->donecount += length;
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}
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else if (request->flags & ATA_R_WRITE) {
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ata_pio_write(request, length);
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request->donecount += length;
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}
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else
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request->status = ATA_S_ERROR;
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/* FALLTHROUGH */
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case ATAPI_P_ABORT:
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case ATAPI_P_DONE:
|
|
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
|
|
request->error = ATA_IDX_INB(ch, ATA_ERROR);
|
|
break;
|
|
|
|
default:
|
|
ata_prtdev(request->device, "unknown transfer phase\n");
|
|
request->status = ATA_S_ERROR;
|
|
}
|
|
|
|
/* done with HW */
|
|
break;
|
|
|
|
/* ATAPI DMA commands */
|
|
case ATA_R_ATAPI|ATA_R_DMA:
|
|
|
|
/* stop the engine and get engine status */
|
|
if (ch->dma->stop)
|
|
request->dmastat = ch->dma->stop(ch);
|
|
|
|
/* did we get error or data */
|
|
if (request->status & (ATA_S_ERROR | ATA_S_DWF))
|
|
request->error = ATA_IDX_INB(ch, ATA_ERROR);
|
|
else if (request->dmastat & ATA_BMSTAT_ERROR)
|
|
request->status |= ATA_S_ERROR;
|
|
else
|
|
request->donecount = request->bytecount;
|
|
|
|
/* release SG list etc */
|
|
ch->dma->unload(ch);
|
|
|
|
/* done with HW */
|
|
break;
|
|
}
|
|
|
|
/* if we timed out the unlocking of the ATA channel is done later */
|
|
if (!(request->flags & ATA_R_TIMEOUT)) {
|
|
ch->running = NULL;
|
|
ATA_UNLOCK_CH(ch);
|
|
ch->locking(ch, ATA_LF_UNLOCK);
|
|
}
|
|
|
|
/* schedule completition for this request */
|
|
ata_finish(request);
|
|
}
|
|
|
|
/* must be called with ATA channel locked */
|
|
static void
|
|
ata_generic_reset(struct ata_channel *ch)
|
|
{
|
|
u_int8_t err, lsb, msb, ostat0, ostat1;
|
|
u_int8_t stat0 = 0, stat1 = 0;
|
|
int mask = 0, timeout;
|
|
|
|
/* reset host end of channel (if supported) */
|
|
if (ch->reset)
|
|
ch->reset(ch);
|
|
|
|
/* do we have any signs of ATA/ATAPI HW being present ? */
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
|
|
DELAY(10);
|
|
ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
|
|
stat0 = ATA_S_BUSY;
|
|
mask |= 0x01;
|
|
}
|
|
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
|
|
DELAY(10);
|
|
ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
|
|
/* in some setups we dont want to test for a slave */
|
|
if (!(ch->flags & ATA_NO_SLAVE)) {
|
|
if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
|
|
stat1 = ATA_S_BUSY;
|
|
mask |= 0x02;
|
|
}
|
|
}
|
|
|
|
/* if nothing showed up there is no need to get any further */
|
|
/* SOS is that too strong?, we just might loose devices here XXX */
|
|
ch->devices = 0;
|
|
if (!mask)
|
|
return;
|
|
|
|
if (bootverbose)
|
|
ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
|
|
mask, ostat0, ostat1);
|
|
|
|
/* reset (both) devices on this channel */
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
|
|
DELAY(10);
|
|
ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET);
|
|
DELAY(10000);
|
|
ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS);
|
|
DELAY(100000);
|
|
ATA_IDX_INB(ch, ATA_ERROR);
|
|
|
|
/* wait for BUSY to go inactive */
|
|
for (timeout = 0; timeout < 310; timeout++) {
|
|
if (stat0 & ATA_S_BUSY) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
|
|
DELAY(10);
|
|
err = ATA_IDX_INB(ch, ATA_ERROR);
|
|
lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
|
|
msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
|
|
stat0 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
if (bootverbose)
|
|
ata_printf(ch, ATA_MASTER,
|
|
"stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
|
|
stat0, err, lsb, msb);
|
|
if (!(stat0 & ATA_S_BUSY)) {
|
|
if ((err & 0x7f) == ATA_E_ILI) {
|
|
if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
|
|
ch->devices |= ATA_ATAPI_MASTER;
|
|
}
|
|
else if (stat0 & ATA_S_READY) {
|
|
ch->devices |= ATA_ATA_MASTER;
|
|
}
|
|
}
|
|
else if ((stat0 & 0x4f) && err == lsb && err == msb) {
|
|
stat0 |= ATA_S_BUSY;
|
|
}
|
|
}
|
|
}
|
|
if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
|
|
DELAY(10);
|
|
err = ATA_IDX_INB(ch, ATA_ERROR);
|
|
lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
|
|
msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
|
|
stat1 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
if (bootverbose)
|
|
ata_printf(ch, ATA_SLAVE,
|
|
" stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
|
|
stat1, err, lsb, msb);
|
|
if (!(stat1 & ATA_S_BUSY)) {
|
|
if ((err & 0x7f) == ATA_E_ILI) {
|
|
if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
|
|
ch->devices |= ATA_ATAPI_SLAVE;
|
|
}
|
|
else if (stat1 & ATA_S_READY) {
|
|
ch->devices |= ATA_ATA_SLAVE;
|
|
}
|
|
}
|
|
else if ((stat1 & 0x4f) && err == lsb && err == msb) {
|
|
stat1 |= ATA_S_BUSY;
|
|
}
|
|
}
|
|
}
|
|
if (mask == 0x01) /* wait for master only */
|
|
if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20))
|
|
break;
|
|
if (mask == 0x02) /* wait for slave only */
|
|
if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20))
|
|
break;
|
|
if (mask == 0x03) { /* wait for both master & slave */
|
|
if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
|
|
break;
|
|
if (stat0 == 0xff && timeout > 20)
|
|
mask &= ~0x01;
|
|
if (stat1 == 0xff && timeout > 20)
|
|
mask &= ~0x02;
|
|
}
|
|
DELAY(100000);
|
|
}
|
|
|
|
if (stat0 & ATA_S_BUSY)
|
|
mask &= ~0x01;
|
|
if (stat1 & ATA_S_BUSY)
|
|
mask &= ~0x02;
|
|
|
|
if (bootverbose)
|
|
ata_printf(ch, -1,
|
|
"reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n",
|
|
mask, stat0, stat1, ch->devices,
|
|
"\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
|
|
}
|
|
|
|
static int
|
|
ata_wait(struct ata_device *atadev, u_int8_t mask)
|
|
{
|
|
u_int8_t status;
|
|
int timeout = 0;
|
|
|
|
DELAY(1);
|
|
|
|
/* wait 5 seconds for device to get !BUSY */
|
|
while (timeout < 5000000) {
|
|
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
|
|
|
|
/* if drive fails status, reselect the drive just to be sure */
|
|
if (status == 0xff) {
|
|
ata_prtdev(atadev, "WARNING no status, reselecting device\n");
|
|
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
|
|
DELAY(10);
|
|
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
|
|
if (status == 0xff)
|
|
return -1;
|
|
}
|
|
|
|
/* are we done ? */
|
|
if (!(status & ATA_S_BUSY))
|
|
break;
|
|
|
|
if (timeout > 1000) {
|
|
timeout += 1000;
|
|
DELAY(1000);
|
|
}
|
|
else {
|
|
timeout += 10;
|
|
DELAY(10);
|
|
}
|
|
}
|
|
if (timeout >= 5000000)
|
|
return -1;
|
|
if (!mask)
|
|
return (status & ATA_S_ERROR);
|
|
|
|
DELAY(1);
|
|
|
|
/* wait 50 msec for bits wanted */
|
|
timeout = 5000;
|
|
while (timeout--) {
|
|
status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
|
|
if ((status & mask) == mask)
|
|
return (status & ATA_S_ERROR);
|
|
DELAY (10);
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
int
|
|
ata_generic_command(struct ata_device *atadev, u_int8_t command,
|
|
u_int64_t lba, u_int16_t count, u_int16_t feature)
|
|
{
|
|
if (atadebug)
|
|
ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, "
|
|
"lba=%jd, count=%d, feature=%d\n",
|
|
rman_get_start(atadev->channel->r_io[ATA_DATA].res),
|
|
command, (intmax_t)lba, count, feature);
|
|
|
|
/* select device */
|
|
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
|
|
|
|
/* ready to issue command ? */
|
|
if (ata_wait(atadev, 0) < 0) {
|
|
ata_prtdev(atadev, "timeout sending command=%02x\n", command);
|
|
return -1;
|
|
}
|
|
|
|
/* enable interrupt */
|
|
ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT);
|
|
|
|
/* only use 48bit addressing if needed (avoid bugs and overhead) */
|
|
if ((lba > 268435455 || count > 256) && atadev->param &&
|
|
atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) {
|
|
|
|
/* translate command into 48bit version */
|
|
switch (command) {
|
|
case ATA_READ:
|
|
command = ATA_READ48; break;
|
|
case ATA_READ_MUL:
|
|
command = ATA_READ_MUL48; break;
|
|
case ATA_READ_DMA:
|
|
command = ATA_READ_DMA48; break;
|
|
case ATA_READ_DMA_QUEUED:
|
|
command = ATA_READ_DMA_QUEUED48; break;
|
|
case ATA_WRITE:
|
|
command = ATA_WRITE48; break;
|
|
case ATA_WRITE_MUL:
|
|
command = ATA_WRITE_MUL48; break;
|
|
case ATA_WRITE_DMA:
|
|
command = ATA_WRITE_DMA48; break;
|
|
case ATA_WRITE_DMA_QUEUED:
|
|
command = ATA_WRITE_DMA_QUEUED48; break;
|
|
case ATA_FLUSHCACHE:
|
|
command = ATA_FLUSHCACHE48; break;
|
|
default:
|
|
ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
|
|
return -1;
|
|
}
|
|
ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit);
|
|
atadev->channel->flags |= ATA_48BIT_ACTIVE;
|
|
}
|
|
else {
|
|
ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
|
|
if (atadev->flags & ATA_D_USE_CHS)
|
|
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
|
|
ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf));
|
|
else
|
|
ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
|
|
ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf));
|
|
atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
|
|
}
|
|
|
|
/* issue command to controller */
|
|
ATA_IDX_OUTB(atadev->channel, ATA_CMD, command);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
ata_pio_read(struct ata_request *request, int length)
|
|
{
|
|
int size = min(request->transfersize, length);
|
|
struct ata_channel *ch = request->device->channel;
|
|
int resid;
|
|
|
|
if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
|
|
ATA_IDX_INSW_STRM(ch, ATA_DATA,
|
|
(void*)((uintptr_t)request->data+request->donecount),
|
|
size / sizeof(int16_t));
|
|
else
|
|
ATA_IDX_INSL_STRM(ch, ATA_DATA,
|
|
(void*)((uintptr_t)request->data+request->donecount),
|
|
size / sizeof(int32_t));
|
|
|
|
if (request->transfersize < length) {
|
|
ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n",
|
|
ata_cmd2str(request), length, request->transfersize);
|
|
for (resid = request->transfersize; resid < length;
|
|
resid += sizeof(int16_t))
|
|
ATA_IDX_INW(ch, ATA_DATA);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ata_pio_write(struct ata_request *request, int length)
|
|
{
|
|
int size = min(request->transfersize, length);
|
|
struct ata_channel *ch = request->device->channel;
|
|
int resid;
|
|
|
|
if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
|
|
ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
|
|
(void*)((uintptr_t)request->data+request->donecount),
|
|
size / sizeof(int16_t));
|
|
else
|
|
ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
|
|
(void*)((uintptr_t)request->data+request->donecount),
|
|
size / sizeof(int32_t));
|
|
|
|
if (request->transfersize < length) {
|
|
ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n",
|
|
ata_cmd2str(request), length, request->transfersize);
|
|
for (resid = request->transfersize; resid < length;
|
|
resid += sizeof(int16_t))
|
|
ATA_IDX_OUTW(ch, ATA_DATA, 0);
|
|
}
|
|
}
|