860 lines
31 KiB
Groff
860 lines
31 KiB
Groff
.\" Automatically generated by Pod::Man v1.3, Pod::Parser v1.13
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.\" ========================================================================
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.\"
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.IX Title "AS 1"
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.TH AS 1 "2002-08-05" "binutils-2.12.91" "GNU Development Tools"
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.UC
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.SH "NAME"
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\&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler.
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
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[\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR]
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[\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR]
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[\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR]
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[\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR]
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[\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB\-\-target\-help\fR] [\fItarget-options\fR]
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[\fB\-\-\fR|\fIfiles\fR ...]
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.PP
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\&\fITarget Alpha options:\fR
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[\fB\-m\fR\fIcpu\fR]
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[\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
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[\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
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[\fB\-F\fR] [\fB\-32addr\fR]
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.PP
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\&\fITarget \s-1ARC\s0 options:\fR
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[\fB\-marc[5|6|7|8]\fR]
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[\fB\-EB\fR|\fB\-EL\fR]
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.PP
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\&\fITarget \s-1ARM\s0 options:\fR
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[\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
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[\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
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[\fB\-mfpu\fR=\fIfloating-point-fromat\fR]
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[\fB\-mthumb\fR]
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[\fB\-EB\fR|\fB\-EL\fR]
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[\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
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\fB\-mapcs\-reentrant\fR]
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[\fB\-mthumb\-interwork\fR] [\fB\-moabi\fR] [\fB\-k\fR]
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.PP
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\&\fITarget \s-1CRIS\s0 options:\fR
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[\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
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[\fB\-\-pic\fR] [\fB\-N\fR]
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[\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
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.PP
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\&\fITarget D10V options:\fR
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[\fB\-O\fR]
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.PP
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\&\fITarget D30V options:\fR
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[\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
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.PP
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\&\fITarget i386 options:\fR
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[\fB\-\-32\fR|\fB\-\-64\fR]
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.PP
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\&\fITarget i960 options:\fR
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[\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
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\fB\-AKC\fR|\fB\-AMC\fR]
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[\fB\-b\fR] [\fB\-no\-relax\fR]
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.PP
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\&\fITarget M32R options:\fR
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[\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
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\fB\-\-W[n]p\fR]
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.PP
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\&\fITarget M680X0 options:\fR
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[\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
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.PP
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\&\fITarget M68HC11 options:\fR
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[\fB\-m68hc11\fR|\fB\-m68hc12\fR]
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[\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
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[\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
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[\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
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.PP
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\&\fITarget \s-1MCORE\s0 options:\fR
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[\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
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[\fB\-mcpu=[210|340]\fR]
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.PP
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\&\fITarget \s-1MIPS\s0 options:\fR
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[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-n\fR] [\fB\-O\fR[\fIoptimization level\fR]]
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[\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
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[\fB\-non_shared\fR] [\fB\-xgot\fR] [\fB\-\-membedded\-pic\fR]
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[\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
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[\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
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[\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips64\fR]
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[\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
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[\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
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[\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
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[\fB\-mips16\fR] [\fB\-no\-mips16\fR]
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[\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
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[\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
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[\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
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.PP
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\&\fITarget \s-1MMIX\s0 options:\fR
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[\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
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[\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
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[\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
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[\fB\-\-linker\-allocated\-gregs\fR]
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.PP
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\&\fITarget \s-1PDP11\s0 options:\fR
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[\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
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[\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
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[\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
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.PP
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\&\fITarget picoJava options:\fR
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[\fB\-mb\fR|\fB\-me\fR]
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.PP
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\&\fITarget PowerPC options:\fR
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[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
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\fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
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\fB\-mbooke32\fR|\fB\-mbooke64\fR]
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[\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
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[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
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[\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
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[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
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[\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
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.PP
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\&\fITarget \s-1SPARC\s0 options:\fR
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[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
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\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
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[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
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[\fB\-32\fR|\fB\-64\fR]
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.SH "DESCRIPTION"
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.IX Header "DESCRIPTION"
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\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
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If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
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should find a fairly similar environment when you use it on another
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architecture. Each version has much in common with the others,
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including object file formats, most assembler directives (often called
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\&\fIpseudo-ops\fR) and assembler syntax.
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.PP
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\&\fBas\fR is primarily intended to assemble the output of the
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\&\s-1GNU\s0 C compiler for use by the linker
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\&. Nevertheless, we've tried to make \fBas\fR
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assemble correctly everything that other assemblers for the same
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machine would assemble.
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Any exceptions are documented explicitly.
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This doesn't mean \fBas\fR always uses the same syntax as another
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assembler for the same architecture; for example, we know of several
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incompatible versions of 680x0 assembly language syntax.
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.PP
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Each time you run \fBas\fR it assembles exactly one source
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program. The source program is made up of one or more files.
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(The standard input is also a file.)
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.PP
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You give \fBas\fR a command line that has zero or more input file
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names. The input files are read (from left file name to right). A
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command line argument (in any position) that has no special meaning
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is taken to be an input file name.
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.PP
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If you give \fBas\fR no file names it attempts to read one input file
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from the \fBas\fR standard input, which is normally your terminal. You
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may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
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to assemble.
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.PP
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Use \fB\-\-\fR if you need to explicitly name the standard input file
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in your command line.
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.PP
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If the source is empty, \fBas\fR produces a small, empty object
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file.
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.PP
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\&\fBas\fR may write warnings and error messages to the standard error
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file (usually your terminal). This should not happen when a compiler
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runs \fBas\fR automatically. Warnings report an assumption made so
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that \fBas\fR could keep assembling a flawed program; errors report a
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grave problem that stops the assembly.
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.PP
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If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler (version 2),
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you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
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The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
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by commas. For example:
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.PP
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.Vb 1
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\& gcc -c -g -O -Wa,-alh,-L file.c
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.Ve
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This passes two options to the assembler: \fB\-alh\fR (emit a listing to
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standard output with with high-level and assembly source) and \fB\-L\fR (retain
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local symbols in the symbol table).
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.PP
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Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
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command-line options are automatically passed to the assembler by the compiler.
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(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
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precisely what options it passes to each compilation pass, including the
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assembler.)
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.SH "OPTIONS"
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.IX Header "OPTIONS"
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.IP "\fB\-a[cdhlmns]\fR" 4
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.IX Item "-a[cdhlmns]"
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Turn on listings, in any of a variety of ways:
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.RS 4
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.IP "\fB\-ac\fR" 4
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.IX Item "-ac"
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omit false conditionals
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.IP "\fB\-ad\fR" 4
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.IX Item "-ad"
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omit debugging directives
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.IP "\fB\-ah\fR" 4
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.IX Item "-ah"
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include high-level source
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.IP "\fB\-al\fR" 4
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.IX Item "-al"
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include assembly
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.IP "\fB\-am\fR" 4
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.IX Item "-am"
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include macro expansions
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.IP "\fB\-an\fR" 4
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.IX Item "-an"
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omit forms processing
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.IP "\fB\-as\fR" 4
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.IX Item "-as"
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include symbols
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.IP "\fB=file\fR" 4
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.IX Item "=file"
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set the name of the listing file
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.RE
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.RS 4
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.Sp
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You may combine these options; for example, use \fB\-aln\fR for assembly
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listing without forms processing. The \fB=file\fR option, if used, must be
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the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
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.RE
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.IP "\fB\-D\fR" 4
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.IX Item "-D"
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Ignored. This option is accepted for script compatibility with calls to
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other assemblers.
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.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
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.IX Item "--defsym sym=value"
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Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
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\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
|
|
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
|
|
.IP "\fB\-f\fR" 4
|
|
.IX Item "-f"
|
|
``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
|
|
compiler output).
|
|
.IP "\fB\-\-gstabs\fR" 4
|
|
.IX Item "--gstabs"
|
|
Generate stabs debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it.
|
|
.IP "\fB\-\-gdwarf2\fR" 4
|
|
.IX Item "--gdwarf2"
|
|
Generate \s-1DWARF2\s0 debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it. Note \- this
|
|
option is only supported by some targets, not all of them.
|
|
.IP "\fB\-\-help\fR" 4
|
|
.IX Item "--help"
|
|
Print a summary of the command line options and exit.
|
|
.IP "\fB\-\-target\-help\fR" 4
|
|
.IX Item "--target-help"
|
|
Print a summary of all target specific options and exit.
|
|
.IP "\fB\-I\fR \fIdir\fR" 4
|
|
.IX Item "-I dir"
|
|
Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
|
|
.IP "\fB\-J\fR" 4
|
|
.IX Item "-J"
|
|
Don't warn about signed overflow.
|
|
.IP "\fB\-K\fR" 4
|
|
.IX Item "-K"
|
|
This option is accepted but has no effect on the \s-1TARGET\s0 family.
|
|
.IP "\fB\-L\fR" 4
|
|
.IX Item "-L"
|
|
.PD 0
|
|
.IP "\fB\-\-keep\-locals\fR" 4
|
|
.IX Item "--keep-locals"
|
|
.PD
|
|
Keep (in the symbol table) local symbols. On traditional a.out systems
|
|
these start with \fBL\fR, but different systems have different local
|
|
label prefixes.
|
|
.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-lhs-width=number"
|
|
Set the maximum width, in words, of the output data column for an assembler
|
|
listing to \fInumber\fR.
|
|
.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-lhs-width2=number"
|
|
Set the maximum width, in words, of the output data column for continuation
|
|
lines in an assembler listing to \fInumber\fR.
|
|
.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-rhs-width=number"
|
|
Set the maximum width of an input source line, as displayed in a listing, to
|
|
\&\fInumber\fR bytes.
|
|
.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-cont-lines=number"
|
|
Set the maximum number of lines printed in a listing for a single line of input
|
|
to \fInumber\fR + 1.
|
|
.IP "\fB\-o\fR \fIobjfile\fR" 4
|
|
.IX Item "-o objfile"
|
|
Name the object-file output from \fBas\fR \fIobjfile\fR.
|
|
.IP "\fB\-R\fR" 4
|
|
.IX Item "-R"
|
|
Fold the data section into the text section.
|
|
.IP "\fB\-\-statistics\fR" 4
|
|
.IX Item "--statistics"
|
|
Print the maximum space (in bytes) and total time (in seconds) used by
|
|
assembly.
|
|
.IP "\fB\-\-strip\-local\-absolute\fR" 4
|
|
.IX Item "--strip-local-absolute"
|
|
Remove local absolute symbols from the outgoing symbol table.
|
|
.IP "\fB\-v\fR" 4
|
|
.IX Item "-v"
|
|
.PD 0
|
|
.IP "\fB\-version\fR" 4
|
|
.IX Item "-version"
|
|
.PD
|
|
Print the \fBas\fR version.
|
|
.IP "\fB\-\-version\fR" 4
|
|
.IX Item "--version"
|
|
Print the \fBas\fR version and exit.
|
|
.IP "\fB\-W\fR" 4
|
|
.IX Item "-W"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-warn\fR" 4
|
|
.IX Item "--no-warn"
|
|
.PD
|
|
Suppress warning messages.
|
|
.IP "\fB\-\-fatal\-warnings\fR" 4
|
|
.IX Item "--fatal-warnings"
|
|
Treat warnings as errors.
|
|
.IP "\fB\-\-warn\fR" 4
|
|
.IX Item "--warn"
|
|
Don't suppress warning messages or treat them as errors.
|
|
.IP "\fB\-w\fR" 4
|
|
.IX Item "-w"
|
|
Ignored.
|
|
.IP "\fB\-x\fR" 4
|
|
.IX Item "-x"
|
|
Ignored.
|
|
.IP "\fB\-Z\fR" 4
|
|
.IX Item "-Z"
|
|
Generate an object file even after errors.
|
|
.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
|
|
.IX Item "-- | files ..."
|
|
Standard input, or source files to assemble.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
an \s-1ARC\s0 processor.
|
|
.IP "\fB\-marc[5|6|7|8]\fR" 4
|
|
.IX Item "-marc[5|6|7|8]"
|
|
This option selects the core processor variant.
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
|
.IX Item "-EB | -EL"
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
|
.PP
|
|
The following options are available when as is configured for the \s-1ARM\s0
|
|
processor family.
|
|
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-mcpu=processor[+extension...]"
|
|
Specify which \s-1ARM\s0 processor variant is the target.
|
|
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-march=architecture[+extension...]"
|
|
Specify which \s-1ARM\s0 architecture variant is used by the target.
|
|
.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
|
|
.IX Item "-mfpu=floating-point-format"
|
|
Select which Floating Point architecture is the target.
|
|
.IP "\fB\-mthumb\fR" 4
|
|
.IX Item "-mthumb"
|
|
Enable Thumb only instruction decoding.
|
|
.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
|
|
.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
|
|
Select which procedure calling convention is in use.
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
|
.IX Item "-EB | -EL"
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
|
.IP "\fB\-mthumb\-interwork\fR" 4
|
|
.IX Item "-mthumb-interwork"
|
|
Specify that the code has been generated with interworking between Thumb and
|
|
\&\s-1ARM\s0 code in mind.
|
|
.IP "\fB\-k\fR" 4
|
|
.IX Item "-k"
|
|
Specify that \s-1PIC\s0 code has been generated.
|
|
.PP
|
|
See the info pages for documentation of the CRIS-specific options.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a D10V processor.
|
|
.IP "\fB\-O\fR" 4
|
|
.IX Item "-O"
|
|
Optimize output by parallelizing instructions.
|
|
.PP
|
|
The following options are available when as is configured for a D30V
|
|
processor.
|
|
.IP "\fB\-O\fR" 4
|
|
.IX Item "-O"
|
|
Optimize output by parallelizing instructions.
|
|
.IP "\fB\-n\fR" 4
|
|
.IX Item "-n"
|
|
Warn when nops are generated.
|
|
.IP "\fB\-N\fR" 4
|
|
.IX Item "-N"
|
|
Warn when a nop after a 32\-bit multiply instruction is generated.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Intel 80960 processor.
|
|
.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
|
|
.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
|
|
Specify which variant of the 960 architecture is the target.
|
|
.IP "\fB\-b\fR" 4
|
|
.IX Item "-b"
|
|
Add code to collect statistics about branches taken.
|
|
.IP "\fB\-no\-relax\fR" 4
|
|
.IX Item "-no-relax"
|
|
Do not alter compare-and-branch instructions for long displacements;
|
|
error if necessary.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Mitsubishi M32R series.
|
|
.IP "\fB\-\-m32rx\fR" 4
|
|
.IX Item "--m32rx"
|
|
Specify which processor in the M32R family is the target. The default
|
|
is normally the M32R, but this option changes it to the M32RX.
|
|
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
|
|
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
|
|
Produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
|
|
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
|
|
Do not produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Motorola 68000 series.
|
|
.IP "\fB\-l\fR" 4
|
|
.IX Item "-l"
|
|
Shorten references to undefined symbols, to one word instead of two.
|
|
.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
|
|
.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
|
|
.PD 0
|
|
.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
|
|
.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
|
|
.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
|
|
.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
|
|
.PD
|
|
Specify what processor in the 68000 family is the target. The default
|
|
is normally the 68020, but this can be changed at configuration time.
|
|
.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
|
|
.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
|
|
The target machine does (or does not) have a floating-point coprocessor.
|
|
The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
|
|
the basic 68000 is not compatible with the 68881, a combination of the
|
|
two can be specified, since it's possible to do emulation of the
|
|
coprocessor instructions with the main processor.
|
|
.IP "\fB\-m68851 | \-mno\-68851\fR" 4
|
|
.IX Item "-m68851 | -mno-68851"
|
|
The target machine does (or does not) have a memory-management
|
|
unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
|
|
.PP
|
|
For details about the \s-1PDP\-11\s0 machine dependent features options,
|
|
see \f(CW@ref\fR{PDP\-11\-Options}.
|
|
.IP "\fB\-mpic | \-mno\-pic\fR" 4
|
|
.IX Item "-mpic | -mno-pic"
|
|
Generate position-independent (or position\-dependent) code. The
|
|
default is \fB\-mpic\fR.
|
|
.IP "\fB\-mall\fR" 4
|
|
.IX Item "-mall"
|
|
.PD 0
|
|
.IP "\fB\-mall\-extensions\fR" 4
|
|
.IX Item "-mall-extensions"
|
|
.PD
|
|
Enable all instruction set extensions. This is the default.
|
|
.IP "\fB\-mno\-extensions\fR" 4
|
|
.IX Item "-mno-extensions"
|
|
Disable all instruction set extensions.
|
|
.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
|
|
.IX Item "-mextension | -mno-extension"
|
|
Enable (or disable) a particular instruction set extension.
|
|
.IP "\fB\-m\fR\fIcpu\fR" 4
|
|
.IX Item "-mcpu"
|
|
Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
|
|
disable all other extensions.
|
|
.IP "\fB\-m\fR\fImachine\fR" 4
|
|
.IX Item "-mmachine"
|
|
Enable the instruction set extensions supported by a particular machine
|
|
model, and disable all other extensions.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a picoJava processor.
|
|
.IP "\fB\-mb\fR" 4
|
|
.IX Item "-mb"
|
|
Generate ``big endian'' format output.
|
|
.IP "\fB\-ml\fR" 4
|
|
.IX Item "-ml"
|
|
Generate ``little endian'' format output.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Motorola 68HC11 or 68HC12 series.
|
|
.IP "\fB\-m68hc11 | \-m68hc12\fR" 4
|
|
.IX Item "-m68hc11 | -m68hc12"
|
|
Specify what processor is the target. The default is
|
|
defined by the configuration option when building the assembler.
|
|
.IP "\fB\-\-force\-long\-branchs\fR" 4
|
|
.IX Item "--force-long-branchs"
|
|
Relative branches are turned into absolute ones. This concerns
|
|
conditional branches, unconditional branches and branches to a
|
|
sub routine.
|
|
.IP "\fB\-S | \-\-short\-branchs\fR" 4
|
|
.IX Item "-S | --short-branchs"
|
|
Do not turn relative branchs into absolute ones
|
|
when the offset is out of range.
|
|
.IP "\fB\-\-strict\-direct\-mode\fR" 4
|
|
.IX Item "--strict-direct-mode"
|
|
Do not turn the direct addressing mode into extended addressing mode
|
|
when the instruction does not support direct addressing mode.
|
|
.IP "\fB\-\-print\-insn\-syntax\fR" 4
|
|
.IX Item "--print-insn-syntax"
|
|
Print the syntax of instruction in case of error.
|
|
.IP "\fB\-\-print\-opcodes\fR" 4
|
|
.IX Item "--print-opcodes"
|
|
print the list of instructions with syntax and then exit.
|
|
.IP "\fB\-\-generate\-example\fR" 4
|
|
.IX Item "--generate-example"
|
|
print an example of instruction for each possible instruction and then exit.
|
|
This option is only useful for testing \fBas\fR.
|
|
.PP
|
|
The following options are available when \fBas\fR is configured
|
|
for the \s-1SPARC\s0 architecture:
|
|
.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
|
|
.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
|
|
.PD 0
|
|
.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
|
|
.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
|
|
.PD
|
|
Explicitly select a variant of the \s-1SPARC\s0 architecture.
|
|
.Sp
|
|
\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
|
|
\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
|
|
.Sp
|
|
\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
|
|
UltraSPARC extensions.
|
|
.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
|
|
.IX Item "-xarch=v8plus | -xarch=v8plusa"
|
|
For compatibility with the Solaris v9 assembler. These options are
|
|
equivalent to \-Av8plus and \-Av8plusa, respectively.
|
|
.IP "\fB\-bump\fR" 4
|
|
.IX Item "-bump"
|
|
Warn when the assembler switches to another architecture.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a \s-1MIPS\s0 processor.
|
|
.IP "\fB\-G\fR \fInum\fR" 4
|
|
.IX Item "-G num"
|
|
This option sets the largest size of an object that can be referenced
|
|
implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
|
|
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
|
|
.IP "\fB\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
Generate ``big endian'' format output.
|
|
.IP "\fB\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
Generate ``little endian'' format output.
|
|
.IP "\fB\-mips1\fR" 4
|
|
.IX Item "-mips1"
|
|
.PD 0
|
|
.IP "\fB\-mips2\fR" 4
|
|
.IX Item "-mips2"
|
|
.IP "\fB\-mips3\fR" 4
|
|
.IX Item "-mips3"
|
|
.IP "\fB\-mips4\fR" 4
|
|
.IX Item "-mips4"
|
|
.IP "\fB\-mips5\fR" 4
|
|
.IX Item "-mips5"
|
|
.IP "\fB\-mips32\fR" 4
|
|
.IX Item "-mips32"
|
|
.IP "\fB\-mips64\fR" 4
|
|
.IX Item "-mips64"
|
|
.PD
|
|
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
|
|
\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
|
|
alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
|
|
\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
|
|
\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond to generic
|
|
\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, and \fB\s-1MIPS64\s0\fR \s-1ISA\s0 processors,
|
|
respectively.
|
|
.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
|
|
.IX Item "-march=CPU"
|
|
Generate code for a particular \s-1MIPS\s0 cpu.
|
|
.IP "\fB\-mtune=\fR\fIcpu\fR" 4
|
|
.IX Item "-mtune=cpu"
|
|
Schedule and tune for a particular \s-1MIPS\s0 cpu.
|
|
.IP "\fB\-mfix7000\fR" 4
|
|
.IX Item "-mfix7000"
|
|
.PD 0
|
|
.IP "\fB\-mno\-fix7000\fR" 4
|
|
.IX Item "-mno-fix7000"
|
|
.PD
|
|
Cause nops to be inserted if the read of the destination register
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
.IP "\fB\-mdebug\fR" 4
|
|
.IX Item "-mdebug"
|
|
.PD 0
|
|
.IP "\fB\-no\-mdebug\fR" 4
|
|
.IX Item "-no-mdebug"
|
|
.PD
|
|
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
|
|
section instead of the standard \s-1ELF\s0 .stabs sections.
|
|
.IP "\fB\-mgp32\fR" 4
|
|
.IX Item "-mgp32"
|
|
.PD 0
|
|
.IP "\fB\-mfp32\fR" 4
|
|
.IX Item "-mfp32"
|
|
.PD
|
|
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
|
|
flags force a certain group of registers to be treated as 32 bits wide at
|
|
all times. \fB\-mgp32\fR controls the size of general-purpose registers
|
|
and \fB\-mfp32\fR controls the size of floating-point registers.
|
|
.IP "\fB\-mips16\fR" 4
|
|
.IX Item "-mips16"
|
|
.PD 0
|
|
.IP "\fB\-no\-mips16\fR" 4
|
|
.IX Item "-no-mips16"
|
|
.PD
|
|
Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting
|
|
\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR
|
|
turns off this option.
|
|
.IP "\fB\-mips3d\fR" 4
|
|
.IX Item "-mips3d"
|
|
.PD 0
|
|
.IP "\fB\-no\-mips3d\fR" 4
|
|
.IX Item "-no-mips3d"
|
|
.PD
|
|
Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
|
|
\&\fB\-no\-mips3d\fR turns off this option.
|
|
.IP "\fB\-mdmx\fR" 4
|
|
.IX Item "-mdmx"
|
|
.PD 0
|
|
.IP "\fB\-no\-mdmx\fR" 4
|
|
.IX Item "-no-mdmx"
|
|
.PD
|
|
Generate code for the \s-1MDMX\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MDMX\s0 instructions.
|
|
\&\fB\-no\-mdmx\fR turns off this option.
|
|
.IP "\fB\-\-construct\-floats\fR" 4
|
|
.IX Item "--construct-floats"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-construct\-floats\fR" 4
|
|
.IX Item "--no-construct-floats"
|
|
.PD
|
|
The \fB\-\-no\-construct\-floats\fR option disables the construction of
|
|
double width floating point constants by loading the two halves of the
|
|
value into the two single width floating point registers that make up
|
|
the double width register. By default \fB\-\-construct\-floats\fR is
|
|
selected, allowing construction of these floating point constants.
|
|
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
|
|
.IX Item "--emulation=name"
|
|
This option causes \fBas\fR to emulate \fBas\fR configured
|
|
for some other target, in all respects, including output format (choosing
|
|
between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
|
|
debugging information or store symbol table information, and default
|
|
endianness. The available configuration names are: \fBmipsecoff\fR,
|
|
\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
|
|
\&\fBmipsbelf\fR. The first two do not alter the default endianness from that
|
|
of the primary target for which the assembler was configured; the others change
|
|
the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
|
|
in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
|
|
selection in any case.
|
|
.Sp
|
|
This option is currently supported only when the primary target
|
|
\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
|
|
Furthermore, the primary target or others specified with
|
|
\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
|
|
the other format, if both are to be available. For example, the Irix 5
|
|
configuration includes support for both.
|
|
.Sp
|
|
Eventually, this option will support more configurations, with more
|
|
fine-grained control over the assembler's behavior, and will be supported for
|
|
more processors.
|
|
.IP "\fB\-nocpp\fR" 4
|
|
.IX Item "-nocpp"
|
|
\&\fBas\fR ignores this option. It is accepted for compatibility with
|
|
the native tools.
|
|
.IP "\fB\-\-trap\fR" 4
|
|
.IX Item "--trap"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-trap\fR" 4
|
|
.IX Item "--no-trap"
|
|
.IP "\fB\-\-break\fR" 4
|
|
.IX Item "--break"
|
|
.IP "\fB\-\-no\-break\fR" 4
|
|
.IX Item "--no-break"
|
|
.PD
|
|
Control how to deal with multiplication overflow and division by zero.
|
|
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
|
|
(and only work for Instruction Set Architecture level 2 and higher);
|
|
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
|
|
break exception.
|
|
.IP "\fB\-n\fR" 4
|
|
.IX Item "-n"
|
|
When this option is used, \fBas\fR will issue a warning every
|
|
time it generates a nop instruction from a macro.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
an MCore processor.
|
|
.IP "\fB\-jsri2bsr\fR" 4
|
|
.IX Item "-jsri2bsr"
|
|
.PD 0
|
|
.IP "\fB\-nojsri2bsr\fR" 4
|
|
.IX Item "-nojsri2bsr"
|
|
.PD
|
|
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled.
|
|
The command line option \fB\-nojsri2bsr\fR can be used to disable it.
|
|
.IP "\fB\-sifilter\fR" 4
|
|
.IX Item "-sifilter"
|
|
.PD 0
|
|
.IP "\fB\-nosifilter\fR" 4
|
|
.IX Item "-nosifilter"
|
|
.PD
|
|
Enable or disable the silicon filter behaviour. By default this is disabled.
|
|
The default can be overridden by the \fB\-sifilter\fR command line option.
|
|
.IP "\fB\-relax\fR" 4
|
|
.IX Item "-relax"
|
|
Alter jump instructions for long displacements.
|
|
.IP "\fB\-mcpu=[210|340]\fR" 4
|
|
.IX Item "-mcpu=[210|340]"
|
|
Select the cpu type on the target hardware. This controls which instructions
|
|
can be assembled.
|
|
.IP "\fB\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
Assemble for a big endian target.
|
|
.IP "\fB\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
Assemble for a little endian target.
|
|
.PP
|
|
See the info pages for documentation of the MMIX-specific options.
|
|
.SH "SEE ALSO"
|
|
.IX Header "SEE ALSO"
|
|
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
|
|
.SH "COPYRIGHT"
|
|
.IX Header "COPYRIGHT"
|
|
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
|
|
.PP
|
|
Permission is granted to copy, distribute and/or modify this document
|
|
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
|
|
or any later version published by the Free Software Foundation;
|
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
|
Back-Cover Texts. A copy of the license is included in the
|
|
section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
|