4a9b01b262
While cause codes higher than 16 are reserved, the exception code field of the register is defined to be all bits but the upper-most bit. Reviewed by: mhorne MFC after: 1 week Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D23510
252 lines
7.4 KiB
C
252 lines
7.4 KiB
C
/*-
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* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_RISCVREG_H_
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#define _MACHINE_RISCVREG_H_
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#define EXCP_MASK (~EXCP_INTR)
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#define EXCP_MISALIGNED_FETCH 0
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#define EXCP_FAULT_FETCH 1
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#define EXCP_ILLEGAL_INSTRUCTION 2
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#define EXCP_BREAKPOINT 3
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#define EXCP_MISALIGNED_LOAD 4
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#define EXCP_FAULT_LOAD 5
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#define EXCP_MISALIGNED_STORE 6
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#define EXCP_FAULT_STORE 7
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#define EXCP_USER_ECALL 8
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#define EXCP_SUPERVISOR_ECALL 9
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#define EXCP_HYPERVISOR_ECALL 10
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#define EXCP_MACHINE_ECALL 11
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#define EXCP_INST_PAGE_FAULT 12
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#define EXCP_LOAD_PAGE_FAULT 13
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#define EXCP_STORE_PAGE_FAULT 15
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#define EXCP_INTR (1ul << 63)
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#define SSTATUS_UIE (1 << 0)
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#define SSTATUS_SIE (1 << 1)
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#define SSTATUS_UPIE (1 << 4)
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#define SSTATUS_SPIE (1 << 5)
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#define SSTATUS_SPIE_SHIFT 5
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#define SSTATUS_SPP (1 << 8)
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#define SSTATUS_SPP_SHIFT 8
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#define SSTATUS_FS_SHIFT 13
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#define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT)
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#define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT)
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#define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT)
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#define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT)
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#define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT)
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#define SSTATUS_XS_SHIFT 15
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#define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT)
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#define SSTATUS_SUM (1 << 18)
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#if __riscv_xlen == 64
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#define SSTATUS_SD (1ul << 63)
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#else
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#define SSTATUS_SD (1 << 31)
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#endif
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#define MSTATUS_UIE (1 << 0)
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#define MSTATUS_SIE (1 << 1)
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#define MSTATUS_HIE (1 << 2)
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#define MSTATUS_MIE (1 << 3)
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#define MSTATUS_UPIE (1 << 4)
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#define MSTATUS_SPIE (1 << 5)
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#define MSTATUS_SPIE_SHIFT 5
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#define MSTATUS_HPIE (1 << 6)
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#define MSTATUS_MPIE (1 << 7)
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#define MSTATUS_MPIE_SHIFT 7
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#define MSTATUS_SPP (1 << 8)
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#define MSTATUS_SPP_SHIFT 8
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#define MSTATUS_HPP_MASK 0x3
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#define MSTATUS_HPP_SHIFT 9
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#define MSTATUS_MPP_MASK 0x3
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#define MSTATUS_MPP_SHIFT 11
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#define MSTATUS_FS_MASK 0x3
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#define MSTATUS_FS_SHIFT 13
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#define MSTATUS_XS_MASK 0x3
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#define MSTATUS_XS_SHIFT 15
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#define MSTATUS_MPRV (1 << 17)
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#define MSTATUS_PUM (1 << 18)
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#define MSTATUS_VM_MASK 0x1f
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#define MSTATUS_VM_SHIFT 24
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#define MSTATUS_VM_MBARE 0
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#define MSTATUS_VM_MBB 1
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#define MSTATUS_VM_MBBID 2
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#define MSTATUS_VM_SV32 8
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#define MSTATUS_VM_SV39 9
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#define MSTATUS_VM_SV48 10
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#define MSTATUS_VM_SV57 11
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#define MSTATUS_VM_SV64 12
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#if __riscv_xlen == 64
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#define MSTATUS_SD (1ul << 63)
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#else
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#define MSTATUS_SD (1 << 31)
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#endif
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#define MSTATUS_PRV_U 0 /* user */
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#define MSTATUS_PRV_S 1 /* supervisor */
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#define MSTATUS_PRV_H 2 /* hypervisor */
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#define MSTATUS_PRV_M 3 /* machine */
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#define MIE_USIE (1 << 0)
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#define MIE_SSIE (1 << 1)
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#define MIE_HSIE (1 << 2)
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#define MIE_MSIE (1 << 3)
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#define MIE_UTIE (1 << 4)
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#define MIE_STIE (1 << 5)
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#define MIE_HTIE (1 << 6)
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#define MIE_MTIE (1 << 7)
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#define MIP_USIP (1 << 0)
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#define MIP_SSIP (1 << 1)
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#define MIP_HSIP (1 << 2)
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#define MIP_MSIP (1 << 3)
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#define MIP_UTIP (1 << 4)
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#define MIP_STIP (1 << 5)
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#define MIP_HTIP (1 << 6)
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#define MIP_MTIP (1 << 7)
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#define SIE_USIE (1 << 0)
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#define SIE_SSIE (1 << 1)
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#define SIE_UTIE (1 << 4)
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#define SIE_STIE (1 << 5)
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#define SIE_UEIE (1 << 8)
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#define SIE_SEIE (1 << 9)
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#define MIP_SEIP (1 << 9)
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/* Note: sip register has no SIP_STIP bit in Spike simulator */
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#define SIP_SSIP (1 << 1)
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#define SIP_STIP (1 << 5)
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#define SATP_PPN_S 0
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#define SATP_PPN_M (0xfffffffffff << SATP_PPN_S)
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#define SATP_ASID_S 44
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#define SATP_ASID_M (0xffff << SATP_ASID_S)
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#define SATP_MODE_S 60
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#define SATP_MODE_M (0xf << SATP_MODE_S)
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#define SATP_MODE_SV39 (8ULL << SATP_MODE_S)
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#define SATP_MODE_SV48 (9ULL << SATP_MODE_S)
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#define XLEN __riscv_xlen
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#define XLEN_BYTES (XLEN / 8)
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#define INSN_SIZE 4
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#define INSN_C_SIZE 2
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#define X_RA 1
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#define X_SP 2
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#define X_GP 3
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#define X_TP 4
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#define X_T0 5
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#define X_T1 6
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#define X_T2 7
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#define X_T3 28
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#define RD_SHIFT 7
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#define RD_MASK (0x1f << RD_SHIFT)
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#define RS1_SHIFT 15
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#define RS1_MASK (0x1f << RS1_SHIFT)
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#define RS1_SP (X_SP << RS1_SHIFT)
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#define RS2_SHIFT 20
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#define RS2_MASK (0x1f << RS2_SHIFT)
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#define RS2_RA (X_RA << RS2_SHIFT)
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#define IMM_SHIFT 20
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#define IMM_MASK (0xfff << IMM_SHIFT)
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#define RS2_C_SHIFT 2
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#define RS2_C_MASK (0x1f << RS2_C_SHIFT)
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#define RS2_C_RA (X_RA << RS2_C_SHIFT)
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#define CSR_ZIMM(val) \
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(__builtin_constant_p(val) && ((u_long)(val) < 32))
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#define csr_swap(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrrwi %0, " #csr ", %1" \
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: "=r" (val) : "i" (val)); \
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else \
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__asm __volatile("csrrw %0, " #csr ", %1" \
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: "=r" (val) : "r" (val)); \
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val; \
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})
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#define csr_write(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
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})
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#define csr_set(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
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})
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#define csr_clear(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
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})
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#define csr_read(csr) \
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({ u_long val; \
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__asm __volatile("csrr %0, " #csr : "=r" (val)); \
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val; \
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})
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#if __riscv_xlen == 32
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#define csr_read64(csr) \
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({ uint64_t val; \
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uint32_t high, low; \
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__asm __volatile("1: " \
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"csrr t0, " #csr "h\n" \
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"csrr %0, " #csr "\n" \
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"csrr %1, " #csr "h\n" \
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"bne t0, %1, 1b" \
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: "=r" (low), "=r" (high) \
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: \
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: "t0"); \
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val = (low | ((uint64_t)high << 32)); \
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val; \
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})
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#else
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#define csr_read64(csr) ((uint64_t)csr_read(csr))
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#endif
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#endif /* !_MACHINE_RISCVREG_H_ */
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