freebsd-dev/sys/conf/options.mips
Brooks Davis f2de4d722e MFP4:
Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08

        Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in
        cache.c into an option and when set force I- and D-cache line
        sizes to 0 (the latter part might be better as a tunable).

        Fix some casts in an #if 0'd bit of code which attempts to
        disable L1 cache ops when the cache is coherent.

Sponsored by:	DARPA/AFRL
2013-10-22 21:16:57 +00:00

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# Copyright (c) 2001, 2008, Juniper Networks, Inc.
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#
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# modification, are permitted provided that the following conditions
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# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the Juniper Networks, Inc. nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY JUNIPER NETWORKS AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL JUNIPER NETWORKS OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# JNPR: options.mips,v 1.2 2006/09/15 12:52:34
# $FreeBSD$
CPU_MIPS4KC opt_global.h
CPU_MIPS24KC opt_global.h
CPU_MIPS74KC opt_global.h
CPU_MIPS32 opt_global.h
CPU_MIPS64 opt_global.h
CPU_SENTRY5 opt_global.h
CPU_HAVEFPU opt_global.h
CPU_SB1 opt_global.h
CPU_CNMIPS opt_global.h
CPU_RMI opt_global.h
CPU_NLM opt_global.h
CPU_BERI opt_global.h
# which MACHINE_ARCH architecture
MIPS
MIPSEL
MIPS64
MIPS64EL
MIPSN32
COMPAT_FREEBSD32 opt_compat.h
YAMON opt_global.h
CFE opt_global.h
CFE_CONSOLE opt_global.h
CFE_ENV opt_global.h
CFE_ENV_SIZE opt_global.h
GFB_DEBUG opt_gfb.h
GFB_NO_FONT_LOADING opt_gfb.h
GFB_NO_MODE_CHANGE opt_gfb.h
NOFPU opt_global.h
TICK_USE_YAMON_FREQ opt_global.h
TICK_USE_MALTA_RTC opt_global.h
#
# The highest memory address that can be used by the kernel in units of KB.
#
MAXMEM opt_global.h
#
# Manual override of cache config
#
MIPS_DISABLE_L1_CACHE opt_global.h
#
# Options that control the Cavium Simple Executive.
#
OCTEON_MODEL opt_cvmx.h
OCTEON_VENDOR_LANNER opt_cvmx.h
OCTEON_VENDOR_UBIQUITI opt_cvmx.h
OCTEON_VENDOR_RADISYS opt_cvmx.h
OCTEON_VENDOR_GEFES opt_cvmx.h
OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
#
# Options specific to the BERI platform.
#
BERI_LARGE_TLB opt_global.h
#
# Options that control the Atheros SoC peripherals
#
ARGE_DEBUG opt_arge.h
ARGE_MDIO opt_arge.h
#
# At least one of the AR71XX ubiquiti boards has a Redboot configuration
# that "lies" about the amount of RAM it has. Until a cleaner method is
# defined, this option will suffice in overriding what Redboot says.
#
AR71XX_REALMEM opt_ar71xx.h
AR71XX_ENV_UBOOT opt_ar71xx.h
AR71XX_ENV_REDBOOT opt_ar71xx.h
AR71XX_ATH_EEPROM opt_ar71xx.h
#
# Options that control the Ralink RT305xF Etherenet MAC.
#
IF_RT_DEBUG opt_if_rt.h
IF_RT_PHY_SUPPORT opt_if_rt.h
IF_RT_RING_DATA_COUNT opt_if_rt.h
#
# Options that affect the pmap.
#
PV_STATS opt_pmap.h