1164 lines
32 KiB
C
1164 lines
32 KiB
C
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/*******************************************************************************
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*
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* Module Name: hwregs - Read/write access functions for the various ACPI
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* control and status registers.
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* $Revision: 81 $
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*
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******************************************************************************/
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/******************************************************************************
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*
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* 1. Copyright Notice
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*
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* Some or all of this work - Copyright (c) 1999, Intel Corp. All rights
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* reserved.
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*
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* 2. License
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*
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* 2.1. This is your license from Intel Corp. under its intellectual property
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* rights. You may have additional license terms from the party that provided
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* you this software, covering your right to use that party's intellectual
|
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* property rights.
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*
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* 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
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* copy of the source code appearing in this file ("Covered Code") an
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* irrevocable, perpetual, worldwide license under Intel's copyrights in the
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* base code distributed originally by Intel ("Original Intel Code") to copy,
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* make derivatives, distribute, use and display any portion of the Covered
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* Code in any form, with the right to sublicense such rights; and
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*
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* 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
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* license (with the right to sublicense), under only those claims of Intel
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* patents that are infringed by the Original Intel Code, to make, use, sell,
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* offer to sell, and import the Covered Code and derivative works thereof
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* solely to the minimum extent necessary to exercise the above copyright
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|
* license, and in no event shall the patent license extend to any additions
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* to or modifications of the Original Intel Code. No other license or right
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* is granted directly or by implication, estoppel or otherwise;
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*
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* The above copyright and patent license is granted only if the following
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* conditions are met:
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*
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* 3. Conditions
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*
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* 3.1. Redistribution of Source with Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
|
|
* Code or modification with rights to further distribute source must include
|
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* the above Copyright Notice, the above License, this list of Conditions,
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* and the following Disclaimer and Export Compliance provision. In addition,
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* Licensee must cause all Covered Code to which Licensee contributes to
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|
* contain a file documenting the changes Licensee made to create that Covered
|
|
* Code and the date of any change. Licensee must include in that file the
|
|
* documentation of any changes made by any predecessor Licensee. Licensee
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|
* must include a prominent statement that the modification is derived,
|
|
* directly or indirectly, from Original Intel Code.
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*
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* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
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|
* Redistribution of source code of any substantial portion of the Covered
|
|
* Code or modification without rights to further distribute source must
|
|
* include the following Disclaimer and Export Compliance provision in the
|
|
* documentation and/or other materials provided with distribution. In
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|
* addition, Licensee may not authorize further sublicense of source of any
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|
* portion of the Covered Code, and must include terms to the effect that the
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|
* license from Licensee to its licensee is limited to the intellectual
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* property embodied in the software Licensee provides to its licensee, and
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* not to intellectual property embodied in modifications its licensee may
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* make.
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*
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* 3.3. Redistribution of Executable. Redistribution in executable form of any
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|
* substantial portion of the Covered Code or modification must reproduce the
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* above Copyright Notice, and the following Disclaimer and Export Compliance
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* provision in the documentation and/or other materials provided with the
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* distribution.
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*
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* 3.4. Intel retains all right, title, and interest in and to the Original
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* Intel Code.
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*
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* 3.5. Neither the name Intel nor any other trademark owned or controlled by
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* Intel shall be used in advertising or otherwise to promote the sale, use or
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* other dealings in products derived from or relating to the Covered Code
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* without prior written authorization from Intel.
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*
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* 4. Disclaimer and Export Compliance
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*
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* 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
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* HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
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* IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
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* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
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* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
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* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
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* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
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* COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
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* SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
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* CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
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* HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
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* SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
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* LIMITED REMEDY.
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*
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* 4.3. Licensee shall not export, either directly or indirectly, any of this
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* software or system incorporating such software without first obtaining any
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* required license or other approval from the U. S. Department of Commerce or
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* any other agency or department of the United States Government. In the
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* event Licensee exports any such software from the United States or
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* re-exports any such software from a foreign destination, Licensee shall
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* ensure that the distribution and export/re-export of the software is in
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* compliance with all laws, regulations, orders, or other restrictions of the
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* U.S. Export Administration Regulations. Licensee agrees that neither it nor
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* any of its subsidiaries will export/re-export any technical data, process,
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* software, or service, directly or indirectly, to any country for which the
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* United States government or any agency thereof requires an export license,
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* other governmental approval, or letter of assurance, without first obtaining
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* such license, approval or letter.
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*
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*****************************************************************************/
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#define __HWREGS_C__
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#include "acpi.h"
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#include "achware.h"
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#include "acnamesp.h"
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#define _COMPONENT HARDWARE
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MODULE_NAME ("hwregs")
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/* This matches the #defines in actypes.h. */
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NATIVE_CHAR *SleepStateTable[] = {"\\_S0_","\\_S1_","\\_S2_","\\_S3_",
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"\\_S4_","\\_S4B","\\_S5_"};
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwGetBitShift
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*
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* PARAMETERS: Mask - Input mask to determine bit shift from.
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* Must have at least 1 bit set.
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*
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* RETURN: Bit location of the lsb of the mask
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*
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* DESCRIPTION: Returns the bit number for the low order bit that's set.
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*
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******************************************************************************/
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static UINT32
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AcpiHwGetBitShift (
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UINT32 Mask)
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{
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UINT32 Shift;
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FUNCTION_TRACE ("HwGetBitShift");
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for (Shift = 0; ((Mask >> Shift) & 1) == 0; Shift++)
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{ ; }
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return_VALUE (Shift);
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}
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwClearAcpiStatus
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*
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* PARAMETERS: none
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*
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* RETURN: none
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*
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* DESCRIPTION: Clears all fixed and general purpose status bits
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*
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******************************************************************************/
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void
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AcpiHwClearAcpiStatus (void)
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{
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UINT16 GpeLength;
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UINT16 Index;
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FUNCTION_TRACE ("HwClearAcpiStatus");
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DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n",
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ALL_FIXED_STS_BITS,
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(UINT16) AcpiGbl_FADT->XPm1aEvtBlk.Address));
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AcpiCmAcquireMutex (ACPI_MTX_HARDWARE);
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AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, PM1_STS, ALL_FIXED_STS_BITS);
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if (AcpiGbl_FADT->XPm1bEvtBlk.Address)
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{
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AcpiOsOut16 ((ACPI_IO_ADDRESS) AcpiGbl_FADT->XPm1bEvtBlk.Address,
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(UINT16) ALL_FIXED_STS_BITS);
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}
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/* now clear the GPE Bits */
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if (AcpiGbl_FADT->Gpe0BlkLen)
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{
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GpeLength = (UINT16) DIV_2 (AcpiGbl_FADT->Gpe0BlkLen);
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for (Index = 0; Index < GpeLength; Index++)
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{
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AcpiOsOut8 ((ACPI_IO_ADDRESS) (AcpiGbl_FADT->XGpe0Blk.Address + Index),
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(UINT8) 0xff);
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}
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}
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if (AcpiGbl_FADT->Gpe1BlkLen)
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{
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GpeLength = (UINT16) DIV_2 (AcpiGbl_FADT->Gpe1BlkLen);
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for (Index = 0; Index < GpeLength; Index++)
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{
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AcpiOsOut8 ((ACPI_IO_ADDRESS) (AcpiGbl_FADT->XGpe1Blk.Address + Index),
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(UINT8) 0xff);
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}
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}
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AcpiCmReleaseMutex (ACPI_MTX_HARDWARE);
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return_VOID;
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}
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwObtainSleepTypeRegisterData
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*
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* PARAMETERS: SleepState - Numeric state requested
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* *Slp_TypA - Pointer to byte to receive SLP_TYPa value
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* *Slp_TypB - Pointer to byte to receive SLP_TYPb value
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*
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* RETURN: Status - ACPI status
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*
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* DESCRIPTION: AcpiHwObtainSleepTypeRegisterData() obtains the SLP_TYP and
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* SLP_TYPb values for the sleep state requested.
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*
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******************************************************************************/
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ACPI_STATUS
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AcpiHwObtainSleepTypeRegisterData (
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UINT8 SleepState,
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UINT8 *Slp_TypA,
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UINT8 *Slp_TypB)
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{
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ACPI_STATUS Status = AE_OK;
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ACPI_OPERAND_OBJECT *ObjDesc;
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FUNCTION_TRACE ("HwObtainSleepTypeRegisterData");
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/*
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* Validate parameters
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*/
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if ((SleepState > ACPI_S_STATES_MAX) ||
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!Slp_TypA || !Slp_TypB)
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{
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return_ACPI_STATUS (AE_BAD_PARAMETER);
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}
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/*
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* AcpiEvaluate the namespace object containing the values for this state
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*/
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Status = AcpiNsEvaluateByName (SleepStateTable[SleepState], NULL, &ObjDesc);
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if (ACPI_FAILURE (Status))
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{
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return_ACPI_STATUS (Status);
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}
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if (!ObjDesc)
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{
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REPORT_ERROR (("Missing Sleep State object\n"));
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return_ACPI_STATUS (AE_NOT_EXIST);
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}
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/*
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* We got something, now ensure it is correct. The object must
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* be a package and must have at least 2 numeric values as the
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* two elements
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*/
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Status = AcpiCmResolvePackageReferences(ObjDesc);
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if (ObjDesc->Package.Count < 2)
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{
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/* Must have at least two elements */
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REPORT_ERROR (("Sleep State package does not have at least two elements\n"));
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Status = AE_ERROR;
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}
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else if (((ObjDesc->Package.Elements[0])->Common.Type !=
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ACPI_TYPE_NUMBER) ||
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((ObjDesc->Package.Elements[1])->Common.Type !=
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ACPI_TYPE_NUMBER))
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{
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/* Must have two */
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REPORT_ERROR (("Sleep State package elements are not both of type Number\n"));
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Status = AE_ERROR;
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}
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else
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{
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/*
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* Valid _Sx_ package size, type, and value
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*/
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*Slp_TypA = (UINT8) (ObjDesc->Package.Elements[0])->Number.Value;
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*Slp_TypB = (UINT8) (ObjDesc->Package.Elements[1])->Number.Value;
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}
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|
|
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if (ACPI_FAILURE (Status))
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{
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DEBUG_PRINT (ACPI_ERROR,
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("SleepTypeRegisterData: Bad Sleep object %p type %X\n",
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ObjDesc, ObjDesc->Common.Type));
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}
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AcpiCmRemoveReference (ObjDesc);
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return_ACPI_STATUS (Status);
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}
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|
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/*******************************************************************************
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*
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* FUNCTION: AcpiHwRegisterBitAccess
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*
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* PARAMETERS: ReadWrite - Either ACPI_READ or ACPI_WRITE.
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* UseLock - Lock the hardware
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* RegisterId - index of ACPI Register to access
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* Value - (only used on write) value to write to the
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* Register. Shifted all the way right.
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*
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* RETURN: Value written to or read from specified Register. This value
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* is shifted all the way right.
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*
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* DESCRIPTION: Generic ACPI Register read/write function.
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*
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******************************************************************************/
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UINT32
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AcpiHwRegisterBitAccess (
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NATIVE_UINT ReadWrite,
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BOOLEAN UseLock,
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UINT32 RegisterId,
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...) /* Value (only used on write) */
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{
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UINT32 RegisterValue = 0;
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UINT32 Mask = 0;
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UINT32 Value = 0;
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FUNCTION_TRACE ("HwRegisterBitAccess");
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|
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if (ReadWrite == ACPI_WRITE)
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{
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va_list marker;
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va_start (marker, RegisterId);
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Value = va_arg (marker, UINT32);
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va_end (marker);
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}
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|
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if (ACPI_MTX_LOCK == UseLock) {
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AcpiCmAcquireMutex (ACPI_MTX_HARDWARE);
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}
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|
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/*
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* Decode the Register ID
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* Register id = Register block id | bit id
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*
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* Check bit id to fine locate Register offset.
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* check Mask to determine Register offset, and then read-write.
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*/
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|
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switch (REGISTER_BLOCK_ID(RegisterId))
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{
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case PM1_STS:
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|
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switch (RegisterId)
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{
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case TMR_STS:
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Mask = TMR_STS_MASK;
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break;
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|
|
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case BM_STS:
|
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Mask = BM_STS_MASK;
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break;
|
|
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|
case GBL_STS:
|
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Mask = GBL_STS_MASK;
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|
break;
|
|
|
|
case PWRBTN_STS:
|
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Mask = PWRBTN_STS_MASK;
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break;
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|
|
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case SLPBTN_STS:
|
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Mask = SLPBTN_STS_MASK;
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break;
|
|
|
|
case RTC_STS:
|
|
Mask = RTC_STS_MASK;
|
|
break;
|
|
|
|
case WAK_STS:
|
|
Mask = WAK_STS_MASK;
|
|
break;
|
|
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|
default:
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Mask = 0;
|
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break;
|
|
}
|
|
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM1_STS);
|
|
|
|
if (ReadWrite == ACPI_WRITE)
|
|
{
|
|
/*
|
|
* Status Registers are different from the rest. Clear by
|
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* writing 1, writing 0 has no effect. So, the only relevent
|
|
* information is the single bit we're interested in, all
|
|
* others should be written as 0 so they will be left
|
|
* unchanged
|
|
*/
|
|
|
|
Value <<= AcpiHwGetBitShift (Mask);
|
|
Value &= Mask;
|
|
|
|
if (Value)
|
|
{
|
|
AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, PM1_STS, (UINT16) Value);
|
|
|
|
RegisterValue = 0;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
case PM1_EN:
|
|
|
|
switch (RegisterId)
|
|
{
|
|
case TMR_EN:
|
|
Mask = TMR_EN_MASK;
|
|
break;
|
|
|
|
case GBL_EN:
|
|
Mask = GBL_EN_MASK;
|
|
break;
|
|
|
|
case PWRBTN_EN:
|
|
Mask = PWRBTN_EN_MASK;
|
|
break;
|
|
|
|
case SLPBTN_EN:
|
|
Mask = SLPBTN_EN_MASK;
|
|
break;
|
|
|
|
case RTC_EN:
|
|
Mask = RTC_EN_MASK;
|
|
break;
|
|
|
|
default:
|
|
Mask = 0;
|
|
break;
|
|
}
|
|
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM1_EN);
|
|
|
|
if (ReadWrite == ACPI_WRITE)
|
|
{
|
|
RegisterValue &= ~Mask;
|
|
Value <<= AcpiHwGetBitShift (Mask);
|
|
Value &= Mask;
|
|
RegisterValue |= Value;
|
|
|
|
AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK, PM1_EN, (UINT16) RegisterValue);
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
case PM1_CONTROL:
|
|
|
|
switch (RegisterId)
|
|
{
|
|
case SCI_EN:
|
|
Mask = SCI_EN_MASK;
|
|
break;
|
|
|
|
case BM_RLD:
|
|
Mask = BM_RLD_MASK;
|
|
break;
|
|
|
|
case GBL_RLS:
|
|
Mask = GBL_RLS_MASK;
|
|
break;
|
|
|
|
case SLP_TYPE_A:
|
|
case SLP_TYPE_B:
|
|
Mask = SLP_TYPE_X_MASK;
|
|
break;
|
|
|
|
case SLP_EN:
|
|
Mask = SLP_EN_MASK;
|
|
break;
|
|
|
|
default:
|
|
Mask = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
/*
|
|
* Read the PM1 Control register.
|
|
* Note that at this level, the fact that there are actually TWO
|
|
* registers (A and B) and that B may not exist, are abstracted.
|
|
*/
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM1_CONTROL);
|
|
|
|
DEBUG_PRINT (TRACE_IO, ("PM1 control: Read 0x%X\n", RegisterValue));
|
|
|
|
if (ReadWrite == ACPI_WRITE)
|
|
{
|
|
RegisterValue &= ~Mask;
|
|
Value <<= AcpiHwGetBitShift (Mask);
|
|
Value &= Mask;
|
|
RegisterValue |= Value;
|
|
|
|
/*
|
|
* SLP_TYPE_x Registers are written differently
|
|
* than any other control Registers with
|
|
* respect to A and B Registers. The value
|
|
* for A may be different than the value for B
|
|
*/
|
|
|
|
AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK,
|
|
PM1_CONTROL, (UINT16) RegisterValue);
|
|
}
|
|
break;
|
|
|
|
|
|
case PM2_CONTROL:
|
|
|
|
switch (RegisterId)
|
|
{
|
|
case ARB_DIS:
|
|
Mask = ARB_DIS_MASK;
|
|
break;
|
|
|
|
default:
|
|
Mask = 0;
|
|
break;
|
|
}
|
|
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, PM2_CONTROL);
|
|
|
|
DEBUG_PRINT (TRACE_IO, ("PM2 control: Read 0x%X from 0x%X\n",
|
|
RegisterValue, AcpiGbl_FADT->XPm2CntBlk.Address));
|
|
|
|
if (ReadWrite == ACPI_WRITE)
|
|
{
|
|
RegisterValue &= ~Mask;
|
|
Value <<= AcpiHwGetBitShift (Mask);
|
|
Value &= Mask;
|
|
RegisterValue |= Value;
|
|
|
|
DEBUG_PRINT (TRACE_IO,
|
|
("About to write %04X to %04X\n", RegisterValue,
|
|
AcpiGbl_FADT->XPm2CntBlk.Address));
|
|
|
|
AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK,
|
|
PM2_CONTROL, (UINT8) (RegisterValue));
|
|
}
|
|
break;
|
|
|
|
|
|
case PM_TIMER:
|
|
|
|
Mask = TMR_VAL_MASK;
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK,
|
|
PM_TIMER);
|
|
DEBUG_PRINT (TRACE_IO, ("PM_TIMER: Read 0x%X from 0x%X\n",
|
|
RegisterValue, AcpiGbl_FADT->XPmTmrBlk.Address));
|
|
|
|
break;
|
|
|
|
|
|
case GPE1_EN_BLOCK:
|
|
case GPE1_STS_BLOCK:
|
|
case GPE0_EN_BLOCK:
|
|
case GPE0_STS_BLOCK:
|
|
|
|
/* Determine the bit to be accessed
|
|
*
|
|
* (UINT32) RegisterId:
|
|
* 31 24 16 8 0
|
|
* +--------+--------+--------+--------+
|
|
* | gpe_block_id | gpe_bit_number |
|
|
* +--------+--------+--------+--------+
|
|
*
|
|
* gpe_block_id is one of GPE[01]_EN_BLOCK and GPE[01]_STS_BLOCK
|
|
* gpe_bit_number is relative from the gpe_block (0x00~0xFF)
|
|
*/
|
|
|
|
Mask = REGISTER_BIT_ID(RegisterId); /* gpe_bit_number */
|
|
RegisterId = REGISTER_BLOCK_ID(RegisterId) | (Mask >> 3);
|
|
Mask = AcpiGbl_DecodeTo8bit [Mask % 8];
|
|
|
|
/*
|
|
* The base address of the GPE 0 Register Block
|
|
* Plus 1/2 the length of the GPE 0 Register Block
|
|
* The enable Register is the Register following the Status Register
|
|
* and each Register is defined as 1/2 of the total Register Block
|
|
*/
|
|
|
|
/*
|
|
* This sets the bit within EnableBit that needs to be written to
|
|
* the Register indicated in Mask to a 1, all others are 0
|
|
*/
|
|
|
|
/* Now get the current Enable Bits in the selected Reg */
|
|
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, RegisterId);
|
|
DEBUG_PRINT (TRACE_IO, ("GPE Enable bits: Read 0x%X from 0x%X\n",
|
|
RegisterValue, RegisterId));
|
|
|
|
if (ReadWrite == ACPI_WRITE)
|
|
{
|
|
RegisterValue &= ~Mask;
|
|
Value <<= AcpiHwGetBitShift (Mask);
|
|
Value &= Mask;
|
|
RegisterValue |= Value;
|
|
|
|
/* This write will put the Action state into the General Purpose */
|
|
/* Enable Register indexed by the value in Mask */
|
|
|
|
DEBUG_PRINT (TRACE_IO, ("About to write %04X to %04X\n",
|
|
RegisterValue, RegisterId));
|
|
AcpiHwRegisterWrite (ACPI_MTX_DO_NOT_LOCK,
|
|
RegisterId, (UINT8) RegisterValue);
|
|
RegisterValue = AcpiHwRegisterRead (ACPI_MTX_DO_NOT_LOCK, RegisterId);
|
|
}
|
|
break;
|
|
|
|
|
|
case SMI_CMD_BLOCK:
|
|
case PROCESSOR_BLOCK:
|
|
/* not used */
|
|
default:
|
|
|
|
Mask = 0;
|
|
break;
|
|
}
|
|
|
|
if (ACPI_MTX_LOCK == UseLock) {
|
|
AcpiCmReleaseMutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
|
|
RegisterValue &= Mask;
|
|
RegisterValue >>= AcpiHwGetBitShift (Mask);
|
|
|
|
DEBUG_PRINT (TRACE_IO, ("Register I/O: returning 0x%X\n", RegisterValue));
|
|
return_VALUE (RegisterValue);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwRegisterRead
|
|
*
|
|
* PARAMETERS: UseLock - Mutex hw access.
|
|
* RegisterId - RegisterID + Offset.
|
|
*
|
|
* RETURN: Value read or written.
|
|
*
|
|
* DESCRIPTION: Acpi register read function. Registers are read at the
|
|
* given offset.
|
|
*
|
|
******************************************************************************/
|
|
|
|
UINT32
|
|
AcpiHwRegisterRead (
|
|
BOOLEAN UseLock,
|
|
UINT32 RegisterId)
|
|
{
|
|
UINT32 Value = 0;
|
|
UINT32 Offset = REGISTER_OFFSET (RegisterId);
|
|
UINT32 BankOffset;
|
|
|
|
FUNCTION_TRACE ("AcpiHwRegisterRead");
|
|
|
|
if (ACPI_MTX_LOCK == UseLock)
|
|
{
|
|
AcpiCmAcquireMutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
|
|
switch (REGISTER_BLOCK_ID(RegisterId))
|
|
{
|
|
case PM1_STS: /* 16-bit access */
|
|
|
|
Value = AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1aEvtBlk, Offset);
|
|
Value |= AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1bEvtBlk, Offset);
|
|
break;
|
|
|
|
|
|
case PM1_EN: /* 16-bit access*/
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Pm1EvtLen);
|
|
Value = AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1aEvtBlk, BankOffset + Offset);
|
|
Value |= AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1bEvtBlk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case PM1_CONTROL: /* 16-bit access */
|
|
|
|
if (RegisterId != SLP_TYPE_B)
|
|
{
|
|
Value |= AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1aCntBlk, 0);
|
|
}
|
|
|
|
if (RegisterId != SLP_TYPE_A)
|
|
{
|
|
Value |= AcpiHwLowLevelRead (16, &AcpiGbl_FADT->XPm1bCntBlk, 0);
|
|
}
|
|
break;
|
|
|
|
|
|
case PM2_CONTROL: /* 8-bit access */
|
|
|
|
Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XPm2CntBlk, Offset);
|
|
break;
|
|
|
|
|
|
case PM_TIMER: /* 32-bit access */
|
|
|
|
Value = AcpiHwLowLevelRead (32, &AcpiGbl_FADT->XPmTmrBlk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE0_STS_BLOCK: /* 8-bit access */
|
|
|
|
Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE0_EN_BLOCK: /* 8-bit access */
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen);
|
|
Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe0Blk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case GPE1_STS_BLOCK: /* 8-bit access */
|
|
|
|
Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE1_EN_BLOCK: /* 8-bit access */
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen);
|
|
Value = AcpiHwLowLevelRead (8, &AcpiGbl_FADT->XGpe1Blk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case SMI_CMD_BLOCK: /* 8bit */
|
|
|
|
Value = (UINT32) AcpiOsIn8 (AcpiGbl_FADT->SmiCmd);
|
|
break;
|
|
|
|
|
|
default:
|
|
Value = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
if (ACPI_MTX_LOCK == UseLock)
|
|
{
|
|
AcpiCmReleaseMutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
return_VALUE (Value);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwRegisterWrite
|
|
*
|
|
* PARAMETERS: UseLock - Mutex hw access.
|
|
* RegisterId - RegisterID + Offset.
|
|
*
|
|
* RETURN: Value read or written.
|
|
*
|
|
* DESCRIPTION: Acpi register Write function. Registers are written at the
|
|
* given offset.
|
|
*
|
|
******************************************************************************/
|
|
|
|
void
|
|
AcpiHwRegisterWrite (
|
|
BOOLEAN UseLock,
|
|
UINT32 RegisterId,
|
|
UINT32 Value)
|
|
{
|
|
UINT32 Offset = REGISTER_OFFSET (RegisterId);
|
|
UINT32 BankOffset;
|
|
|
|
FUNCTION_TRACE ("AcpiHwRegisterWrite");
|
|
|
|
|
|
if (ACPI_MTX_LOCK == UseLock)
|
|
{
|
|
AcpiCmAcquireMutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
|
|
switch (REGISTER_BLOCK_ID (RegisterId))
|
|
{
|
|
case PM1_STS: /* 16-bit access */
|
|
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1aEvtBlk, Offset);
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1bEvtBlk, Offset);
|
|
break;
|
|
|
|
|
|
case PM1_EN: /* 16-bit access*/
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Pm1EvtLen);
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1aEvtBlk, BankOffset + Offset);
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1bEvtBlk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case PM1_CONTROL: /* 16-bit access */
|
|
|
|
/*
|
|
* If SLP_TYP_A or SLP_TYP_B, only write to one reg block.
|
|
* Otherwise, write to both.
|
|
*/
|
|
if (RegisterId == SLP_TYPE_A)
|
|
{
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1aCntBlk, Offset);
|
|
}
|
|
else if (RegisterId == SLP_TYPE_B)
|
|
{
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1bCntBlk, Offset);
|
|
}
|
|
else
|
|
{
|
|
/* disable/re-enable interrupts if sleeping */
|
|
if (RegisterId == SLP_EN)
|
|
{
|
|
disable();
|
|
}
|
|
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1aCntBlk, Offset);
|
|
AcpiHwLowLevelWrite (16, Value, &AcpiGbl_FADT->XPm1bCntBlk, Offset);
|
|
|
|
if (RegisterId == SLP_EN)
|
|
{
|
|
enable();
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
case PM2_CONTROL: /* 8-bit access */
|
|
|
|
AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XPm2CntBlk, Offset);
|
|
break;
|
|
|
|
|
|
case PM_TIMER: /* 32-bit access */
|
|
|
|
AcpiHwLowLevelWrite (32, Value, &AcpiGbl_FADT->XPmTmrBlk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE0_STS_BLOCK: /* 8-bit access */
|
|
|
|
AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE0_EN_BLOCK: /* 8-bit access */
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Gpe0BlkLen);
|
|
AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe0Blk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case GPE1_STS_BLOCK: /* 8-bit access */
|
|
|
|
AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, Offset);
|
|
break;
|
|
|
|
|
|
case GPE1_EN_BLOCK: /* 8-bit access */
|
|
|
|
BankOffset = DIV_2 (AcpiGbl_FADT->Gpe1BlkLen);
|
|
AcpiHwLowLevelWrite (8, Value, &AcpiGbl_FADT->XGpe1Blk, BankOffset + Offset);
|
|
break;
|
|
|
|
|
|
case SMI_CMD_BLOCK: /* 8bit */
|
|
|
|
/* For 2.0, SMI_CMD is always in IO space */
|
|
/* TBD: what about 1.0? 0.71? */
|
|
|
|
AcpiOsOut8 (AcpiGbl_FADT->SmiCmd, (UINT8) Value);
|
|
break;
|
|
|
|
|
|
default:
|
|
Value = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
if (ACPI_MTX_LOCK == UseLock)
|
|
{
|
|
AcpiCmReleaseMutex (ACPI_MTX_HARDWARE);
|
|
}
|
|
|
|
return_VOID;
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwLowLevelRead
|
|
*
|
|
* PARAMETERS: Register - GAS register structure
|
|
* Offset - Offset from the base address in the GAS
|
|
* Width - 8, 16, or 32
|
|
*
|
|
* RETURN: Value read
|
|
*
|
|
* DESCRIPTION: Read from either memory, IO, or PCI config space.
|
|
*
|
|
******************************************************************************/
|
|
|
|
UINT32
|
|
AcpiHwLowLevelRead (
|
|
UINT32 Width,
|
|
ACPI_GAS *Reg,
|
|
UINT32 Offset)
|
|
{
|
|
UINT32 Value = 0;
|
|
ACPI_PHYSICAL_ADDRESS MemAddress;
|
|
ACPI_IO_ADDRESS IoAddress;
|
|
UINT32 PciRegister;
|
|
UINT32 PciDevFunc;
|
|
|
|
|
|
/*
|
|
* Must have a valid pointer to a GAS structure, and
|
|
* a non-zero address within
|
|
*/
|
|
if ((!Reg) ||
|
|
(!Reg->Address))
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Three address spaces supported:
|
|
* Memory, Io, or PCI config.
|
|
*/
|
|
|
|
switch (Reg->AddressSpaceId)
|
|
{
|
|
case ADDRESS_SPACE_SYSTEM_MEMORY:
|
|
|
|
MemAddress = (ACPI_PHYSICAL_ADDRESS) Reg->Address + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
Value = AcpiOsMemIn8 (MemAddress);
|
|
break;
|
|
case 16:
|
|
Value = AcpiOsMemIn16 (MemAddress);
|
|
break;
|
|
case 32:
|
|
Value = AcpiOsMemIn32 (MemAddress);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_SYSTEM_IO:
|
|
|
|
IoAddress = (ACPI_IO_ADDRESS) Reg->Address + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
Value = AcpiOsIn8 (IoAddress);
|
|
break;
|
|
case 16:
|
|
Value = AcpiOsIn16 (IoAddress);
|
|
break;
|
|
case 32:
|
|
Value = AcpiOsIn32 (IoAddress);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_PCI_CONFIG:
|
|
|
|
PciDevFunc = ACPI_PCI_DEVFUN (Reg->Address);
|
|
PciRegister = ACPI_PCI_REGISTER (Reg->Address) + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
AcpiOsReadPciCfgByte (0, PciDevFunc, PciRegister, (UINT8 *) &Value);
|
|
break;
|
|
case 16:
|
|
AcpiOsReadPciCfgWord (0, PciDevFunc, PciRegister, (UINT16 *) &Value);
|
|
break;
|
|
case 32:
|
|
AcpiOsReadPciCfgDword (0, PciDevFunc, PciRegister, (UINT32 *) &Value);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return Value;
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: AcpiHwLowLevelWrite
|
|
*
|
|
* PARAMETERS: Width - 8, 16, or 32
|
|
* Value - To be written
|
|
* Register - GAS register structure
|
|
* Offset - Offset from the base address in the GAS
|
|
*
|
|
*
|
|
* RETURN: Value read
|
|
*
|
|
* DESCRIPTION: Read from either memory, IO, or PCI config space.
|
|
*
|
|
******************************************************************************/
|
|
|
|
void
|
|
AcpiHwLowLevelWrite (
|
|
UINT32 Width,
|
|
UINT32 Value,
|
|
ACPI_GAS *Reg,
|
|
UINT32 Offset)
|
|
{
|
|
ACPI_PHYSICAL_ADDRESS MemAddress;
|
|
ACPI_IO_ADDRESS IoAddress;
|
|
UINT32 PciRegister;
|
|
UINT32 PciDevFunc;
|
|
|
|
|
|
/*
|
|
* Must have a valid pointer to a GAS structure, and
|
|
* a non-zero address within
|
|
*/
|
|
if ((!Reg) ||
|
|
(!Reg->Address))
|
|
{
|
|
return;
|
|
}
|
|
|
|
|
|
/*
|
|
* Three address spaces supported:
|
|
* Memory, Io, or PCI config.
|
|
*/
|
|
|
|
switch (Reg->AddressSpaceId)
|
|
{
|
|
case ADDRESS_SPACE_SYSTEM_MEMORY:
|
|
|
|
MemAddress = (ACPI_PHYSICAL_ADDRESS) Reg->Address + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
AcpiOsMemOut8 (MemAddress, (UINT8) Value);
|
|
break;
|
|
case 16:
|
|
AcpiOsMemOut16 (MemAddress, (UINT16) Value);
|
|
break;
|
|
case 32:
|
|
AcpiOsMemOut32 (MemAddress, (UINT32) Value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_SYSTEM_IO:
|
|
|
|
IoAddress = (ACPI_IO_ADDRESS) Reg->Address + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
AcpiOsOut8 (IoAddress, (UINT8) Value);
|
|
break;
|
|
case 16:
|
|
AcpiOsOut16 (IoAddress, (UINT16) Value);
|
|
break;
|
|
case 32:
|
|
AcpiOsOut32 (IoAddress, (UINT32) Value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
|
|
case ADDRESS_SPACE_PCI_CONFIG:
|
|
|
|
PciDevFunc = ACPI_PCI_DEVFUN (Reg->Address);
|
|
PciRegister = ACPI_PCI_REGISTER (Reg->Address) + Offset;
|
|
|
|
switch (Width)
|
|
{
|
|
case 8:
|
|
AcpiOsWritePciCfgByte (0, PciDevFunc, PciRegister, (UINT8) Value);
|
|
break;
|
|
case 16:
|
|
AcpiOsWritePciCfgWord (0, PciDevFunc, PciRegister, (UINT16) Value);
|
|
break;
|
|
case 32:
|
|
AcpiOsWritePciCfgDword (0, PciDevFunc, PciRegister, (UINT32) Value);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
|