d6141d33bc
The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with a 5 port FE switch, gige WAN port, and all the same stuff you'd find on its predecessor - the AR9331. However, buried deep in here somewhere is also a PCIe EP/RC for various applications and some other weird bits I don't yet know about. This is enough to get the reference board up and booting. I haven't yet had it pass lots of packets - I need to finalise the ethernet switch bits and the GMAC configuration (ie, how the ethernet ports and switch are wired up) and I'll bring that in when I commit the base configuration files to use the thing. The wifi stuff will come much later. I have to port that support from Linux ath9k and extend our vendor HAL to support it. The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order to use it I need to get USB working fully so I can run root from there. Thankyou to Qualcomm Atheros for access to the reference design board. Details: * Add register definitions from openwrt; * It looks like a QCA955x but shrunk down to a QCA933x footprint, so use the QCA955x bits and fix up the clock detection code to do the QCA953x bits (they're very subtly different); * Teach GPIO about it; * Teach EHCI about it; * Teach if_arge about it; * Teach the CPU detection code about it. Tested: * AP143, QCA9533v2 SoC Obtained from: Linux, Linux OpenWRT
196 lines
7.6 KiB
C
196 lines
7.6 KiB
C
/*-
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* Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCA953XREG_H__
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#define __QCA953XREG_H__
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#define BIT(x) (1 << (x))
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/* Revision ID information */
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#define REV_ID_MAJOR_QCA9533 0x0140
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#define REV_ID_MAJOR_QCA9533_V2 0x0160
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#define QCA953X_REV_ID_REVISION_MASK 0xf
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/* Big enough to cover APB and SPI, and most peripherals */
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/*
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* it needs to cover SPI because right now the if_ath_ahb
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* code uses rman to map in the SPI address into memory
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* to read data instead of us squirreling it away at early
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* boot-time and using the firmware interface.
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*
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* if_ath_ahb.c should use the same firmware interface
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* that if_ath_pci.c uses.
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*/
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#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define QCA953X_GMAC_SIZE 0x14
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#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA953X_WMAC_SIZE 0x20000
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#define QCA953X_EHCI_BASE 0x1b000000
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#define QCA953X_EHCI_SIZE 0x200
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#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define QCA953X_SRIF_SIZE 0x1000
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#define QCA953X_PCI_CFG_BASE0 0x14000000
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#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
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#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
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#define QCA953X_PCI_MEM_BASE0 0x10000000
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#define QCA953X_PCI_MEM_SIZE 0x02000000
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/* PLL Block */
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#define QCA953X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
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#define QCA953X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04)
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#define QCA953X_PLL_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
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#define QCA953X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c)
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#define QCA953X_PLL_ETH_SGMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x48)
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#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
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#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
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#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
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#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
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#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
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#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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#define QCA953X_PLL_VAL_1000 0x16000000
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#define QCA953X_PLL_VAL_100 0x00000101
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#define QCA953X_PLL_VAL_10 0x00001616
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/* Reset block */
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#define QCA953X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c)
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#define QCA953X_RESET_USB_EXT_PWR BIT(29)
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#define QCA953X_RESET_EXTERNAL BIT(28)
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#define QCA953X_RESET_RTC BIT(27)
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#define QCA953X_RESET_FULL_CHIP BIT(24)
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#define QCA953X_RESET_GE1_MDIO BIT(23)
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#define QCA953X_RESET_GE0_MDIO BIT(22)
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#define QCA953X_RESET_CPU_NMI BIT(21)
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#define QCA953X_RESET_CPU_COLD BIT(20)
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#define QCA953X_RESET_DDR BIT(16)
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#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
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#define QCA953X_RESET_GE1_MAC BIT(13)
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#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
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#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
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#define QCA953X_RESET_GE0_MAC BIT(9)
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#define QCA953X_RESET_ETH_SWITCH BIT(8)
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#define QCA953X_RESET_PCIE_PHY BIT(7)
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#define QCA953X_RESET_PCIE BIT(6)
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#define QCA953X_RESET_USB_HOST BIT(5)
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#define QCA953X_RESET_USB_PHY BIT(4)
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#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
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#define QCA953X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0)
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#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
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#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
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#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
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#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
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#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
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#define QCA953X_RESET_REG_EXT_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac)
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#define QCA953X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
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#define QCA953X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
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#define QCA953X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
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#define QCA953X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
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#define QCA953X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
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/* GPIO block */
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#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
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#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
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#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
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#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
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#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
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#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
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#define QCA953X_GPIO_REG_FUNC 0x6c
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#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
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#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
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#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
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#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
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#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
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#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
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#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
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#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
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#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
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#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
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#define QCA953X_GPIO_COUNT 18
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/* GMAC block */
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#define QCA953X_GMAC_REG_ETH_CFG (QCA953X_GMAC_BASE + 0x00)
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#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
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#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
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#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
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#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
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/* SRIF block */
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#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
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#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
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#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
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#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
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#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
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#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
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#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
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#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
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#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
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#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
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#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
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#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
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#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
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#endif /* __QCA953XREG_H__ */
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